ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 16

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
Table 8. Pin Definitions—External Port SDRAM Controller (Continued)
Table 9. Pin Definitions—JTAG Port
1
Signal
SDA10
SDCKE
SDWE
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5 k
pull-up 500
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
Signal
EMU
TCK
TDI
TDO
TMS
TRST
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5 k
pull-up 500
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
See the reference
Ω
Ω
; pu = internal pull-up 5 k
; pu = internal pull-up 5 k
Ω
Ω
Ω
Ω
to V
to V
on DSP ID = 0; pd_m = internal pull-down 5 k
on DSP ID = 0; pd_m = internal pull-down 5 k
on Page 11
DD_IO
DD_IO
, nc = not connected; na = not applicable (always used); V
, nc = not connected; na = not applicable (always used); V
Ω
Ω
to the JTAG emulation technical reference EE-68.
. For more pull-down and pull-up information, see
. For more pull-down and pull-up information, see
Type
O/T
(pu_0)
I/O/T
(pu_m/
pd_m)
I/O/T
(pu_0)
Type
O/OD
I
I (pu_ad)
O/T
I (pu_ad)
I/A (pu_ad)
Ω
Ω
; pd_0 = internal pull-down 5 k
; pd_0 = internal pull-down 5 k
Term
nc
nc
nc
Term
nc
epd or epu
nc
nc
nc
na
1
1
1
1
Rev. C | Page 16 of 48 | December 2006
1
Description
SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while
the DSP executes non-SDRAM transactions.
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend
modes. A slave DSP in a multiprocessor system does not have the pull-up or pull-
down. A master DSP (or ID = 0 in a single processor system) has a pull-up before
granting the bus to the host, except when the SDRAM is put in self refresh mode. In
self refresh mode, the master has a pull-down before granting the bus to the host.
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to
execute according to SDRAM specification.
Description
Emulation. Connected to the DSP’s JTAG emulator target board connector only.
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
Test Data Input (JTAG). A serial data input of the scan path.
Test Data Output (JTAG). A serial data output of the scan path.
Test Mode Select (JTAG). Used to control the test state machine.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low
after power-up for proper device operation. For more information, see
Booting on Page
Ω
Ω
Ω
Ω
on DSP bus master; pu_m = internal pull-up 5 k
on DSP bus master; pu_m = internal pull-up 5 k
on DSP ID = 0; pu_0 = internal pull-up 5 k
on DSP ID = 0; pu_0 = internal pull-up 5 k
9.
Electrical Characteristics on Page
Electrical Characteristics on Page
DD_IO
DD_IO
= connect directly to V
= connect directly to V
Ω
Ω
to V
to V
Ω
Ω
on DSP ID = 0; pu_od_0 = internal
on DSP ID = 0; pu_od_0 = internal
SS
SS
DD_IO
DD_IO
; epu = external pull-up approx-
; epu = external pull-up approx-
22.
22.
Ω
Ω
; V
; V
on DSP bus master; pu_ad
on DSP bus master; pu_ad
SS
SS
= connect directly to V
= connect directly to V
Reset and
SS
SS