ADSP-21266SKBC-2B AD [Analog Devices], ADSP-21266SKBC-2B Datasheet - Page 21
ADSP-21266SKBC-2B
Manufacturer Part Number
ADSP-21266SKBC-2B
Description
SHARC Embedded Processor
Manufacturer
AD [Analog Devices]
Datasheet
1.ADSP-21266SKBC-2B.pdf
(44 pages)
- Current page: 21 of 44
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Timer PWM_OUT Cycle Timing
The timing specification in
Timer in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DAI_P20
Therefore, the timing specifications provided below are valid at
the DAI_P20
Table 15. Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The timing specification in
Timer in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DAI_P20
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20
Table 16. Timer Width Capture Timing
Parameter
Switching Characteristic
t
Parameter
Timing Requirement
t
PWMO
PWI
DAI_P20–1
DAI_P20–1
(TIMER)
(TIMER)
–
1 pins.
Timer Pulse Width Output
Timer Pulse Width
–
1 pins.
Table 15
Table 16
–
1 pins through the SRU.
and
and
–
Figure 12
Figure 13
1 pins through the
Figure 13. Timer Width Capture Timing
applies to
applies to
Figure 12. Timer PWM_OUT Timing
Rev. B | Page 21 of 44 | May 2005
Min
2 t
Min
2 t
CCLK
CCLK
t
PWMO
– 1
t
PWI
Max
2(2
Max
2(2
31
31
– 1) t
– 1) t
CCLK
CCLK
ADSP-21266
Unit
ns
Unit
ns
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