ADSP-21262_05 AD [Analog Devices], ADSP-21262_05 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21262_05
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-21262
Table 25. Serial Ports—Enable and Three-State
1
Table 26. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
The t
This figure reflects changes made to support left-justified sample pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
NOTE: SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P201
(SCLK)
(SCLK)
(FS)
(FS)
1
DRIVE
DRIVE
t
DDTLFSE
t
DDTLFSE
1
Figure 21. External Late Frame Sync
Rev. B | Page 30 of 48 | August 2005
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
t
SFSE/I
SFSE/I
t
LATE EXTERNAL TRANSMIT FS
DDTENFS
t
DDTENFS
1
1
1
SAMPLE
SAMPLE
1ST BIT
DATA CHANNEL
1ST BIT
t
HDTE/I
t
HDTE/I
DRIVE
DRIVE
A/B) ARE ROUTED TO THE DAI_P[20:1] PINS
t
t
HFSE/I
HFSE/I
1
Min
2
–1
Min
0.5
t
DDTE/I
t
DDTE/I
2ND BIT
2ND BIT
Max
7
Max
7
Unit
ns
ns
ns
Unit
ns
ns