ADSP-1981BL AD [Analog Devices], ADSP-1981BL Datasheet - Page 12

• Manufacturer Part Number: ADSP-1981BL
• Description: AC 97 SoundMAX Codec
• Manufacturer: AD [Analog Devices]

AD1981BL
INDEXED CONTROL REGISTERS
Table 8.
Reg
0x00
0x02
0x04
0x06
0x0C
0x0E
0x10
0x12
0x16
0x18
0x1A
0x1C
0x20
0x26
0x28
0x2A
0x2C
0x32
0x3A
0x60
0x62
0x64
0x72
0x74
0x76
0x7C
0x7E
1
For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown. Bits containing an X are assumed to be reserved.
Name
Reset
Master
Volume
Headphone
Volume
Mono
Volume
Phone
Volume
MIC Volume
Line-In
Volume
CD Volume
AUX Volume
PCM-Out
Volume
Record
Select
Record Gain
General-
Purpose
Power-Down
Ctrl/Stat
Ext’d Audio
ID
Ext’d Audio
Stat/Ctrl
PCM Front
DAC Rate
PCM L/R
ADC Rate
SPDIF
Control
EQ Ctrl
EQ Data
Mixer ADC,
Volume
Jack Sense
Serial Config
Misc Control
Bit
Vendor ID1
Vendor ID2
D15
X
MM
HPM
MVM
PHM
MCM
LVM
CVM
AM
OM
X
IM
X
EAPD
IDC1
VFORCE
SRF15
SRA15
V
EQM
CFD15
MXM
X
SLOT 16
DACZ
F7
T7
D14
SE4
X
X
X
X
X
X
X
X
X
X
X
X
PR6
IDC0
X
SRF14
SRA14
X
MAD
LBEN
CFD14
X
X
REGM 2
X
F6
T6
X
F5
D13
SE3
X
X
X
X
X
X
X
X
X
X
X
X
PR5
X
SRF13
SRA13
SPSR1
X
CFD13
X
X
REGM 1
MSPLT
T5
D12
SE2
LMV4
LHV4
X
X
X
LLV4
LCV4
LAV4
LOV4
X
X
X
PR4
X
X
SRF12
SRA12
SPSR0
X
CFD12
X
JS MT2
REGM 0
LODIS
F4
T4
D11
SE1
LMV3
LHV3
X
X
X
LLV3
LCV3
LAV3
LOV3
X
LIM3
X
PR3
REVC1
X
SRF11
SRA11
L
X
CFD11
LMG3
JS
MT1
X
DAM
F3
T3
D10
SE0
LMV2
LHV2
X
X
X
LLV2
LCV2
LAV2
LOV2
LS2
LIM2
X
PR2
REVC0
SPCV
SRF10
SRA10
CC6
X
CFD10
LMG2
JS
MT0
X
X
F2
T2
Rev. A | Page 12 of 32
D9
LMV1
LHV1
X
X
X
LLV1
LCV1
LAV1
LOV1
LS1
LIM1
MIX
PR1
AMAP
X
SRA9
CC5
X
LMG1
JS1
EQB
X
FMXE
F1
T1
ID9
SRF9
CFD9
X
X
F0
D8
ID8
LMV0
LHV0
X
X
X
LLV0
LCV0
LAV0
LOV0
LS0
LIM0
MS
PR0
SRF8
SRA8
CC4
X
CFD8
LMG0
JS0
EQB
CHEN
X
T0
X
S7
D7
ID7
RM
RM
X
X
X
RM
RM
RM
RM
X
RM
LPBK
X
X
SRF7
SRA7
CC3
SYM
CFD7
RM
JS1
TMR
X
MAD
PD
REV7
1
1
1
1
1
1
1
1
X
D6
ID6
X
X
X
X
M20
X
X
X
X
X
X
X
X
X
SRF6
SRA6
CC2
CHS
CFD6
X
JS0
TMR
X
2CMIC
S6
REV6
D5
ID5
X
X
X
X
X
X
X
X
X
X
X
X
X
DSA1
SPSA1
SRF5
SRA5
CC1
BCA5
CFD5
X
JS1
MD
X
X
S5
REV5
D4
ID4
RMV4
RHV4
MV4
PHV4
MCV4
RLV4
RCV4
RAV4
ROV4
X
X
X
X
DSA0
SPSA0
SRF4
SRA4
CC0
BCA4
CFD4
X
JS0
MD
INTS
MAD
ST
S4
REV4
D3
ID3
RMV3
RHV3
MV3
PHV3
MCV3
RLV3
RCV3
RAV3
ROV3
X
RIM3
X
REF
X
X
SRF3
SRA3
PRE
BCA3
CFD3
RMG3
JS1
ST
X
VREFH
S3
REV3
D2
ID2
RMV2
RHV2
MV2
PHV2
MCV2
RLV2
RCV2
RAV2
ROV2
RS2
RIM2
X
ANL
SPDIF
SPDIF
SRF2
SRA2
COPY
BCA2
CFD2
RMG2
JS0 ST
SPAL
VREFD
S2
REV2
D1
ID1
RMV1
RHV1
MV1
PHV1
MCV1
RLV1
RCV1
RAV1
ROV1
RS1
RIM1
X
DAC
X
X
SRF1
SRA1
/AUD
BCA1
CFD1
RMG1
JS1
INT
SPDZ
MBG1
S1
REV1
D0
ID0
RMV0
RHV0
MV0
PHV0
MCV0
RLV0
RCV0
RAV0
ROV0
RS0
RIM0
X
ADC
VRAS
VRA
SRF0
SRA0
PRO
BCA0
CFD0
RMG0
JS0
INT
SPLNK
MBG0
S0
REV0
Default
0x0090
0x8000
0x8000
0x8000
0x8008
0x8008
0x8808
0x8808
0x8808
0x8808
0x0000
0x8000
0x0000
0x000X
0xX605
0x0000
0xBB80
0xBB80
0x2000
0x8080
0x0000
0x8000
0x0000
0x7001
0x0000
0x4144
0x5374