XCR3032-10PC44C XILINX [Xilinx, Inc], XCR3032-10PC44C Datasheet - Page 5

• Manufacturer Part Number: XCR3032-10PC44C
• Description: 32 Macrocell CPLD
• Manufacturer: XILINX [Xilinx, Inc]

This product has been discontinued. Please see
XCR3032: 32 Macrocell CPLD
Simple Timing Model
Figure 5
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
may be able to fit the design into the CPLD, but is not sure
whether system timing requirements can be met until after
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sharable expand-
ers, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR3032 device, the user knows up front that if a given
output uses five product terms or less, the t
Figure 4: CoolRunner Timing Model
5
shows the CoolRunner Timing Model. The Cool-
PD
, t
GLOBAL CLOCK PIN
SU
, and t
INPUT PIN
INPUT PIN
CO
. In other architectures, the user
t
t
SU_PLA
SU_PAL
REGISTERED
PD
= PAL ONLY
= PAL + PLA
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= 8 ns, the
t
t
PD_PLA
PD_PAL
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1-800-255-7778
= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA
D
t
37 product terms, an additional 2.5 ns must be added to the
t
propagate through the PLA array.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Frequency of our XCR3032 TotalCMOS CPLD.
SU
PD
= 6.5 ns, and the t
and t
Q
SU
timing parameters to account for the time to
REGISTERED
Figure 6
t
CO
CO
for details.
= 7.5 ns. If an output is using six to
and
DS038 (v1.3) October 9, 2000
Table 1
OUTPUT PIN
OUTPUT PIN
SP00441
showing the I
CC
vs.
R