DAC1208D750HN NXP [NXP Semiconductors], DAC1208D750HN Datasheet - Page 88

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DAC1208D750HN

Manufacturer Part Number
DAC1208D750HN
Description
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
Table 199. LN3_CFG_11 register (address 1Bh) bit description
Default settings are shown highlighted.
Table 200. LN3_CFG_12 register (address 1Ch) bit description
Default settings are shown highlighted.
Table 201. LN3_CFG_13 register (address 1Dh) bit description
Default settings are shown highlighted.
Table 202. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
DAC1208D750
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
2 to 0
Symbol
LN3_RES1[7:0]
Symbol
LN3_RES2[7:0]
Symbol
LN3_FCHK[7:0]
Symbol
PAGE[2:0]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 December 2010
Access
R
Access
R
Access
R
Access
R/W
Value
-
Value
-
Value
Value
0h
-
2×, 4× or 8× interpolating DAC with JESD204A
Description
lane 3 reserved field
Description
lane 3 reserved field
Description
Description
page_address
lane 3 checksum
DAC1208D750
© NXP B.V. 2010. All rights reserved.
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