ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 29

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

C/W0 BIT DESCRIPTION
CGMS Data Bits (C/W03–C/W00)
These four data bits are the final four bits of CGMS data output
stream. Note it is CGMS data ONLY in these bit positions, i.e.,
WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (“1”), the last six bits of the CGMS
data, i.e., the CRC check sequence, is calculated internally by
the ADV7170/ADV7171. If this bit is disabled (“0”) the CRC
values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (“1”), CGMS is enabled for odd fields.
Note this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (“1”), CGMS is enabled for even fields.
Note this is only valid in NTSC mode.
WSS Control (C/W07)
When this bit is set (“1”), wide screen signaling is enabled. Note
this is only valid in PAL mode.
REV. 0
C/W07
WIDE SCREEN SIGNAL
0
1
C/W17
C/W27
CGMS DATA ONLY
CONTROL
TC07
TC07 TC06
C/W17 C/W16
DISABLE
ENABLE
0
0
"
1
1
C/W07
TTXREQ RISING EDGE CONTROL
C/W06
0
0
1
1
"
CGMS EVEN FIELD
C/W16
C/W26
0
1
TC06
CONTROL
TC05 TC04
0
0
"
1
1
C/W06
DISABLE
ENABLE
Figure 50. Teletext Control Register
Figure 51. CGMS_WSS Register 0
Figure 52. CGMS_WSS Register 1
Figure 53. CGMS_WSS Register 2
C/W05
0
1
0
1
"
CGMS ODD FIELD
C/W15
C/W25
TC05
0
1
CONTROL
C/W05
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
DISABLE
ENABLE
C/W14
C/W24
TC04
CGMS/WSS DATA
C/W04
CGMS CRC CHECK
C/W27–C/W20
0
1
C/W04
–29–
CONTROL
DISABLE
ENABLE
CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10)
(Address [SR4–SR0] = 17H)
CGMS_WSS register 1 is an 8-bit-wide register. Figure 52
shows the operations under the control of this register.
C/W1 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W15–C/W10)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
CGMS Data Bits (C/W17–C/W16)
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 C/W1 (C/W27–C/W20)
(Address [SR4–SR0] = 18H)
CGMS_WSS register 2 is an 8-bit-wide register. Figure 53
shows the operations under the control of this register.
C/W2 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W27–C/W20)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
C/W13
C/W23
TC03
CGMS/WSS DATA
TC03 TC02
C/W15–C/W10
0
0
"
1
1
TTXREQ FALLING EDGE CONTROL
C/W03
0
0
"
1
1
C/W12
C/W22
TC02
TC01 TC00
0
0
"
1
1
C/W02
CGMS DATA BITS
C/W03–C/W00
0
1
"
0
1
C/W11
C/W21
TC01
C/W01
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TC00
C/W10
C/W20
ADV7170/ADV7171
C/W00