ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 27

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7170/ADV7171 is in master
or slave mode.
Timing Mode Control (TR02–TR01)
These bits control the timing mode of the ADV7170/ADV7171.
These modes are described in more detail in the Timing and
Control section of the data sheet.
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay Control (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Select (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on Pins
P7–P0.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
REV. 0
TR17 TR16
FIELD/VSYNC
TIMING MODE 1 (MASTER/PAL)
0
0
1
1
DATA ADJUSTMENT
HSYNC TO PIXEL
HSYNC
0
1
0
1
TR17
0
1
2
3
T
T
T
T
PCLK
PCLK
PCLK
PCLK
TR16
T
LINE 1
B
T
A
TR15 TR14
TR15 TR14
0
0
1
1
x
x
RISING EDGE DELAY
HSYNC TO FIELD
(MODE 2 ONLY)
VSYNC WIDTH
(MODE 1 ONLY)
TR15
Figure 44. Timing Register 1
0
1
0
1
0
1
1
4
16
128
T
T
B
B
T
T
T
+ 32 s
TR14
T
C
PCLK
PCLK
T
PCLK
PCLK
–27–
TR13 TR12
TIMING REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 08H)
Timing Register 1 is a 8-bit-wide register.
Figure 44 shows the various operations under the control of
Timing Register 1. This register can be read from as well writ-
ten to. This register can be used to adjust the width and position
of the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulsewidth.
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Delay Control (TR15–TR14)
When the ADV7170/ADV7171 is in timing mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
VSYNC Width (TR15–TR14)
When the ADV7170/ADV7171 is configured in Timing Mode
2, these bits adjust the VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
0
0
1
1
TR13
FIELD/VSYNC DELAY
HSYNC TO
0
1
0
1
TR12
0
4
8
16
T
T
T
T
T
B
PCLK
PCLK
PCLK
T
C
LINE 313
PCLK
TR11
TR11 TR10
0
0
1
1
HSYNC WIDTH
0
1
0
1
LINE 314
TR10
ADV7170/ADV7171
1
4
16
128
T
T
T
A
PCLK
PCLK
T
T
PCLK
PCLK