ADV7121KN30 AD [Analog Devices], ADV7121KN30 Datasheet - Page 6

• Manufacturer Part Number: ADV7121KN30
• Description: CMOS 80 MHz, Triple 10-Bit Video DACs
• Manufacturer: AD [Analog Devices]

Pin
Mnemonic
BLANK*
SYNC*
CLOCK
R0–R9,
G0–G9,
B0–B9
IOR, IOG, IOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
FS ADJUST
COMP
V
V
GND
*SYNC and BLANK functions are not provided on the ADV7121.
ADV7121/ADV7122
REF
AA
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a logical zero, the R0–R9, G0–G9 and R0–R9 pixel inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE
current source. This is internally connected to the IOG analog output. SYNC does not override any other
control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the
rising edge of CLOCK.
If sync information is not required on the green channel, the SYNC input should be tied to logical zero.
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be
driven by a dedicated TTL buffer.
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.
doubly terminated 75
they are all being used.
Full-scale adjust control. A resistor (R
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between R
is given by:
The relationship between R
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used, i.e., SYNC
tied permanently low. For the ADV7121, all three analog output currents are as described by:
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 F ceramic capacitor
must be connected between COMP and V
Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. The use of an
external resistor divider network is not recommended. A 0.1 F decoupling ceramic capacitor should be
connected between V
Analog power supply (5 V
Ground. All GND pins must be connected.
Function
R
IOG* (mA)
IOR, IOB (mA)
IOR, IOG, IOB (mA)
SET
( )
REF
coaxial cable. All three current outputs should have similar output loads whether or not
and V
SET
SET
5%). All V
AA
and the full-scale output current on IOG (assuming I
and the full-scale output current on IOR, IOG and IOB is given by:
PIN FUNCTION DESCRIPTION
.
= 12,082
= 8,628
= 7,969
SET
= 12,082
AA
) connected between this pin and GND, controls the magnitude of the
AA
pins on the ADV7121/ADV7122 must be connected.
.
–6–
V
V
V
REF
REF
V
REF
REF
(V)/R
(V)/R
(V)/R
(V)/IOG (mA)
SET
SET
SET
( )
( )
( ) (SYNC being asserted)
SYNC
is connected to IOG)
REV. B