ADV7121KN30 AD [Analog Devices], ADV7121KN30 Datasheet - Page 11

• Manufacturer Part Number: ADV7121KN30
• Description: CMOS 80 MHz, Triple 10-Bit Video DACs
• Manufacturer: AD [Analog Devices]

Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 8).
Optimum performance is achieved by the use of 0.1 F ceramic
capacitors. Each of the two groups of V
decoupled to ground. This should be done by placing the ca-
pacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV7121/ADV7122 con-
tains circuitry to reject power supply noise, this rejection de-
creases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduce
ing power supply noise. A dc power supply filter (Murata
BNX002) will provide EMI suppression between the switching
power supply and the main PCB. Alternatively, consideration
could be given to using a three terminal voltage regulator.
Digital Signal Interconnect
The digital signal lines to the ADV7121/ADV7122 should be
isolated as much as possible from the analog outputs and other
analog circuitry. Digital signal lines should not overlay the ana-
log power plane.
Due to the high clock rates used, long clock lines to the
ADV7121/ADV7122 should be avoided so as to minimize noise
pickup.
REV. B
INPUTS
CONTROL
VIDEO
DATA
INPUTS
VIDEO
Figure 8. ADV7121/ADV7122 Typical Connection Diagram and Component List
C3, C4, C5, C6
COMPONENT
R1, R2, R3
ADV7121/ADV7122
R0
R9
G0
G9
B0
B9
CLOCK
BLANK*
SYNC*
L1, L2
R
SET
C1
C2
Z1
FS ADJUST
AA
DESCRIPTION
33 F TANTALUM CAPACITOR
10 F TANTALUM
0.1 F CERAMIC CAPACITOR
FERRITE BEAD
75 1% METAL FILM RESISTOR
560 1% METAL FILM RESISTOR
1.235V VOLTAGE REFERENCE
should be individually
COMP
V
GND
V
IOR
IOG
IOB
REF
AA
*SYNC and BLANK FUNCTIONS ARE NOT PROVIDED ON THE ADV7121.
R
560
SET
C6
0.1 F
C3
0.1 F
75
ANALOG POWER PLANE
R1
C4
0.1 F
–11–
75
R2
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (V
and not the analog power plane.
Analog Signal Interconnect
The ADV7121/ADV7122 should be located as close as possible
to the output connectors thus minimizing noise pickup and re-
flections due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75
terminated 75
should be as close as possible to the ADV7121/ADV7122 so as
to minimize reflections.
Additional information on PCB design is available in an appli-
cation note entitled “Design and Layout of a Video Graphics
System for Reduced EMI.” This application note is available
from Analog Devices, publication no. E1309–15–10/89.
VENDOR PART NUMBER
FAIR-RITE 274300111 OR MURATA BL01/02/03
DALE CMF-55C
DALE CMF-55C
ANALOG DEVICES AD589JH
ANALOG GROUND PLANE
C5
0.1 F
75
Z1 (AD589)
R3
configuration). This termination resistance
L1 (FERRITE BEAD)
L2 (FERRITE BEAD)
C2
10 F
ADV7121/ADV7122
RGB
VIDEO
OUTPUT
C1
33 F
+5V (V
GROUND
CC
)
(doubly
CC
),