PCA9510AD PHILIPS [NXP Semiconductors], PCA9510AD Datasheet

PCA9510AD

Manufacturer Part Number

PCA9510AD

Description

Hot swappable I2C-bus and SMBus bus buffer

Manufacturer

PHILIPS [NXP Semiconductors]

Datasheet

1.PCA9510AD.pdf (23 pages)

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1. General description

2. Features

The PCA9510A is a hot swappable I

insertion into a live backplane without corrupting the data and clock buses. Control

circuitry prevents the backplane from being connected to the card until a stop command or

bus idle occurs on the backplane without bus contention on the card. When the

connection is made, the PCA9510A provides bidirectional buffering, keeping the

backplane and card capacitances isolated.

The PCA9510A has no rise time accelerator circuitry to prevent interference when there

are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE

input pin, which enables the device when asserted HIGH and forces the device into a Low

current mode when asserted LOW, and an open-drain READY output pin, which indicates

that the backplane and card sides are connected together (HIGH) or not (LOW).

During insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to

1 V to minimize the current required to charge the parasitic capacitance of the chip.

Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow

them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in

parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot

connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side

or P82B96 Sx/y side.

PCA9510A

Hot swappable I

Rev. 01 — 8 September 2005

Bidirectional buffer for SDA and SCL lines increases fanout and prevents SDA and

SCL corruption during live board insertion and removal from multi-point backplane

systems

Compatible with I

Active HIGH ENABLE input

Active HIGH READY open-drain output

High-impedance SDAn and SCLn pins for V

1 V precharge on SDAIN and SCLIN inputs

Supports clock stretching and multiple master arbitration and synchronization

Operating power supply voltage range: 2.7 V to 5.5 V

I/Os are not 5.5 V tolerant

0 Hz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO8, TSSOP8 (MSOP8)

C-bus Standard mode, I

C-bus and SMBus bus buffer

C-bus and SMBus buffer that allows I/O card

C-bus Fast mode, and SMBus standards

= 0 V

Product data sheet

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