UDA1360 PHILIPS [NXP Semiconductors], UDA1360 Datasheet - Page 5

• Manufacturer Part Number: UDA1360
• Description: Low-voltage low-power stereo audio ADC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 1 Application modes using input gain stage
Multiple format output interface
The UDA1360TS supports the following data output
formats;
The output format can be set by the static SFOR pin. When
SFOR is LOW, the I
HIGH the MSB-justified format is selected.
The data formats are illustrated in Fig.4. Left and right data
channel words are time multiplexed.
Decimation filter
The decimation from 128f
The first stage realizes 3rd-order sin x/x characteristic.
This filter decreases the sample rate by 16. The second
stage (an FIR filter) consists of 3 half-band filters, each
decimating by a factor of 2.
Table 2 DC cancellation filter characteristics
2000 Feb 08
Pass-band ripple
Pass-band gain
Stop band
Droop
Attenuation at DC
Dynamic range
RESISTOR
I
MSB-justified serial format with data word length of up to
20 bits.
Low-voltage low-power stereo audio ADC
2
Present
Present
(12 k )
Absent
Absent
S-bus with data word length of up to 20 bits
ITEM
INPUT GAIN
SWITCH
2
0 dB
6 dB
0 dB
6 dB
S-bus is selected, when SFOR is set
>0.55f
at 0.00045f
at 0.00000036f
0 to 0.45f
CONDITION
s
is performed in two stages.
s
s
s
MAXIMUM INPUT
s
0.5 V (RMS)
2 V (RMS)
1 V (RMS)
1 V (RMS)
VOLTAGE
none
0
0.031
>40
>110
60
VALUE
(dB)
5
Mute
On recovery from power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:
Power-down mode
The PWON pin can control the power saving together with
the optional gain switch for 2 V (RMS) or 1 V (RMS) input.
When the PWON pin is set LOW, the ADC is set to
power-down. When PWON is set to HIGH or to half the
power supply, then either 6 dB gain or 0 dB gain in the
analog front-end is selected.
Application modes
The UDA1360TS can be set to different modes using two
3-level pins and one 2-level pin. The selection of modes is
given in Table 3.
Table 3 Mode selection summary
t
SFOR
PWON
FSEL
=
12288
--------------- -
PIN
f
s
=
279 ms
I
power-down 0 dB gain
256f
2
S-bus
V
s
SS
; where f
test mode
s
= 44.1 kHz.
1
Preliminary specification
2
V
UDA1360TS
DD
MSB
6 dB gain
384f
V
s
DD