UDA1321H PHILIPS [NXP Semiconductors], UDA1321H Datasheet - Page 10
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UDA1321H
Manufacturer Part Number
UDA1321H
Description
Universal Serial Bus USB Digital-to-Analog Converter DAC
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.UDA1321H.pdf
(44 pages)
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Philips Semiconductors
FUNCTIONAL DESCRIPTION
All bold-faced parameters given in this data sheet
such as ‘bAlternateSetting’ are part of the USB
specification as described in “USB Device Class
Definition for Audio Devices” .
The Universal Serial Bus (USB)
Data and power are transferred via the USB by a 4-wire
cable. The signalling occurs via two wires and
point-to-point segments. The signals on each segment are
differentially driven into a cable of 90
impedance. The differential receiver features input
sensitivity of at least 200 mV and sufficient common mode
rejection.
The analog front-end
The analog front-end is an on-chip generic USB
transceiver. It is designed to allow voltage levels up to V
from standard or programmable logic to interface with the
physical layer of the USB. It is capable of receiving and
transmitting serial data at full speed (12 Mbits/s).
The USB processor
The USB processor forms the interface between the
analog front-end, the ADAC and the microcontroller.
The USB processor consists of:
T
M
The PSIE and MMU translate the electrical USB signals
into bytes and signals. Depending upon the USB device
address and the USB endpoint address, the USB data is
directed to the correct endpoint buffer on the PSIE and
MMU interface. The data transfer could be of the bulk,
isochronous, control or interrupt type. The USB device
address is configured during the enumeration process.
The UDA1321 has three endpoints. These are:
The amount of bytes per packet on the control endpoint is
limited by the PSIE and MMU hardware to 8 bytes per
packet.
1998 Oct 06
HE
ANAGEMENT
The Philips Serial Interface Engine (PSIE)
The Memory Management Unit (MMU)
The Audio Sample Redistribution (ASR) module.
Control endpoint 0
Status interrupt endpoint
Isochronous data sink endpoint.
Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)
P
HILIPS
S
ERIAL
U
NIT
(PSIE
I
NTERFACE
AND
MMU)
E
NGINE AND
intrinsic
M
EMORY
DD
10
The PSIE is the digital front-end of the USB processor.This
module recovers the 12 MHz USB clock, detects the USB
sync word and handles all low-level USB protocols and
error checking.
The MMU is the digital back-end of the USB processor.
It handles the temporary data storage of all USB packets
that are received or sent over the bus. Three types of
packets are defined on the USB. These are:
The token packet contains information about the
destination of the data packet. The audio data is
transferred via an isochronous data sink endpoint and
consequently no handshaking mechanism is used.
The MMU also generates a 1 kHz clock that is locked to
the USB Start-Of-Frame (SOF) token.
T
The ASR module reads the audio samples from the MMU
and distributes these samples equidistant over a 1 ms
frame period. The distributed audio samples are translated
by the digital I/O module to standard I
Japanese digital I/O format. The ASR module generates
the bit clock and the word select signal of the digital I/O.
The digital I/O formats the received audio samples to one
of the four specified serial digital audio formats
(standard I
The microcontroller
The microcontroller receives the control information
selected from the USB by the USB processor. It handles
the high-level USB protocols and the user interfaces.
The major task of the software process, that is mapped
upon the microcontroller, is to control the different modules
of the UDA1321 in such a way that it behaves as a USB
device. Therefore the microcontroller:
HE
Token packets
Data packets
Handshake packets.
Interprets the USB requests and maps them upon the
UDA1321 application
Controls the internal operation of the UDA1321 and the
digital I/O pins
Communicates with the external world (EEPROM) using
the I
A
UDIO
2
C-bus facility and the general purpose I/O pins.
2
S
S-bus, 16, 18 or 20 bits LSB-justified).
AMPLE
R
EDISTRIBUTION
Preliminary specification
(ASR)
2
S-bus format or
UDA1321
MODULE