AT84AD001BCTD ATMEL [ATMEL Corporation], AT84AD001BCTD Datasheet - Page 18
AT84AD001BCTD
Manufacturer Part Number
AT84AD001BCTD
Description
Dual 8-bit 1 Gsps ADC
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT84AD001BCTD.pdf
(60 pages)
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Figure 13. Data Ready Reset 1:2 DMUX Mode
Notes:
18
1. In 1:2 DMUX, Fs/2 mode:
2. In 1:2 DMUX, Fs/4 mode:
CLKOI or CLKOQ
CLKOI or CLKOQ
AT84AD001B
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is low, it goes high only when its half cycle is complete; if the reset occurs when it is high, it remains
high) and then only, remains in reset state (frozen to a high level in 1:2 DMUX Fs/2 mode). The next rising edge of the input
clock after reset makes the output clock return to normal mode (after TDR).
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low)
and then only, remains in reset state (frozen to a low level in 1:2 DMUX Fs/4 mode). The next rising edge of the input clock
after reset makes the output clock return to normal mode (after TDR).
DOIA[0:7] or
DOIB[0:7] or
DOQA[0:7]
DOQB[0:7]
(= CLKI/2)
(= CLKI/4)
CLKI or
DDRB
CLKQ
VIN
TA
1 ns min
Clock in
Reset
2 ns
N
N + 1
TDR
TDR
Pipeline Delay + TDO
TDR + 2 cycles
TDR + 2 cycles
N
N + 1
2153C–BDC–04/04
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