MAX6884ETP MAXIM [Maxim Integrated Products], MAX6884ETP Datasheet - Page 27

• Manufacturer Part Number: MAX6884ETP
• Description: EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
• Manufacturer: MAXIM [Maxim Integrated Products]

Both SCL and SDA idle high when the bus is not busy. A
master device signals the beginning of a transmission
with a START (S) condition (see
SDA from high to low while SCL is high. The master
device issues a STOP (P) condition (see
transitioning SDA from low to high while SCL is high. A
STOP condition frees the bus for another transmission.
The bus remains active if a REPEATED START condition
is generated, such as in the block read protocol (see
Figure
The MAX6884/MAX6885 recognize a STOP condition at
any point during transmission except if a STOP condition
occurs in the same high pulse as a START condition.
This condition is not a legal I
pulse must separate any START and STOP condition.
A REPEATED START (SR) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation (see
when the bus master is writing to several I
and does not want to relinquish control of the bus. The
MAX6884/MAX6885 serial interface supports continu-
ous write operations with or without an SR condition
separating them. Continuous read operations require
SR conditions because of the change in direction of
data flow.
Figure
TRANSMITTER
RECEIVER
SDA BY
SDA BY
9. Acknowledge
11).
SCL
CONDITION
START
S
______________________________________________________________________________________
Figure
Repeated START Conditions
2
Start and Stop Conditions
11). SR may also be used
C format; at least one clock
Early STOP Conditions
Figure
Power-Supply Supervisory Circuits
1
8) by transitioning
Figure
2
C devices
EEPROM-Programmable, Hex
8) by
2
The acknowledge bit (ACK) is the 9th bit attached to any
8-bit data word. The receiving device always generates
an ACK. The MAX6884/MAX6885 generate an ACK
when receiving an address or data by pulling SDA low
during the 9th clock period (see
mitting data, such as when the master device reads data
back from the MAX6884/MAX6885, the MAX6884/
MAX6885 wait for the master device to generate an ACK.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
the receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master should reattempt communication at a
later time. The MAX6884/MAX6885 generate a NACK
after the command byte during a software reboot, while
writing to the EEPROM, or when receiving an illegal
memory address.
The MAX6884/MAX6885 slave address conforms to the
following table:
X = Don’t care.
(MSB)
SA7
1
CLOCK PULSE FOR ACKNOWLEDGE
SA6
0
SA5
1
8
SA4
0
SA3
0
Figure
SA2
A0
Slave Address
9). When trans-
Acknowledge
9
SA1
X
(LSB)
SA0
R/W
27