HI3-5700A-9 INTERSIL [Intersil Corporation], HI3-5700A-9 Datasheet - Page 8

• Manufacturer Part Number: HI3-5700A-9
• Description: 8-Bit, 20 MSPS Flash A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

X’s = Don’t Care.
Theory of Operation
The HI-5700 is an 8-bit analog-to-digital converter based on
a parallel CMOS “flash” architecture. This flash technique is
an extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 256 comparators
are used in the HI-5700: (2
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
CE1
X
0
1
CLK
D7
D6
D5
D4
1
V
GND
3
D3
D2
D1
D0
OVF
CE2
CE1
V
AV
AGND
AGND
AV
1
AV
AGND
AGND
AV
V
V
NAME
/
/
/
TABLE 2. CHIP ENABLE TRUTH TABLE
DD
REF
REF
IN
4
4
2
R
R
R
DD
DD
DD
DD
+
-
CE2
TABLE 1. PIN DESCRIPTION
1
1
0
Clock Input
Bit 7, Output (MSB)
Bit 6, Output
Bit 5, Output
Bit 4, Output
1
Digital Power Supply
Digital Ground
3
Bit 3, Output
Bit 2, Output
Bit 1, Output
Bit 0, Output (LSB)
Overflow, Output
Three-State Output Enable Input, Active High.
(See Table 2)
Three-State Output Enable Input, Active Low.
(See Table 2)
Reference Voltage Positive Input
Analog Power Supply, +5V
Analog Ground
Analog Ground
Analog Power Supply, +5V
1
Analog Power Supply, +5V
Analog Ground
Analog Ground
Analog Power Supply, +5V
Reference Voltage Negative Input
Analog Input
/
/
/
4
4
2
th Point of Reference Ladder
th Point of Reference Ladder
Point of Reference Ladder
Valid
Three-State
Three-State
8
-1) comparators to encode the
D0
DESCRIPTION
-
D7
Valid
Valid
Three-State
OVF
HI-5700
4-1498
output word, plus an additional comparator to detect an
overflow condition.
The CMOS HI-5700 works by alternately switching between
a “Sample” mode and an “Auto Balance” mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each
conversion cycle such that offset voltage drift is virtually
eliminated during operation. The block diagram and timing
diagram illustrate how the HI-5700 CMOS flash converter
operates.
The input clock which controls the operation of the HI-5700
is first split into a non-inverting φ1 clock and an inverting φ2
clock. These two clocks, in turn, synchronize all internal
timing of analog switches and control logic within the
converter.
In the “Auto Balance” mode (φ1), all φ1 switches close and
φ2 switches open. The output of each comparator is
momentarily tied to its own input, self-biasing the comparator
midway between GND and V
impedance to a small input capacitor. Each capacitor, in
turn, is connected to a reference voltage tap from the
resistor ladder. The Auto Balance mode quickly precharges
all 256 input capacitors between the self-bias voltage and
each respective tap voltage.
In the “Sample” mode (φ2), all φ1 switches open and φ2
switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The φ2 state
also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage
difference between the reference tap and input voltage to
the comparator input. All 256 comparators are thus driven
simultaneously to a defined logic state. For example, if the
input voltage is at mid-scale, capacitors precharged near
zero during φ1 will push comparator inputs higher than the
self bias voltage at φ2; capacitors precharged near the
reference voltage push the respective comparator inputs
lower than the bias point. In general, all capacitors
precharged by taps above the input voltage force a “low”
voltage at comparator inputs; those precharged below the
input voltage force “high” inputs at the comparators.
During the next φ1 Auto-Balancing state, comparator output
data is latched into the encoder logic block and the first
stage of encoding takes place. The following φ2 state
completes the encoding process. The 8 data bits (plus
overflow bit) are latched into the output flip-flops at the next
falling clock edge. The Overflow bit is set if the input voltage
exceeds V
enabled or disabled according to the state of CE1 and CE2
(See Table 2). When disabled, output bits assume a high
impedance state.
As shown in the timing diagram, the digital output word
becomes valid after the second φ1 state. There is thus a one
and a half cycle pipeline delay between input sample and
digital output. “Data Output Delay” time indicates the slight
time delay for data to become valid at the end of the φ1
REF
+ - 0.5 LSB. The output bus may be either
DD
and presenting a low