HI5760/6IA INTERSIL [Intersil Corporation], HI5760/6IA Datasheet - Page 15

• Manufacturer Part Number: HI5760/6IA
• Description: 10-Bit, 125/60MSPS, High Speed D/A Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Digital Inputs and Termination
The HI5760 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are 50 lines, then 50 termination resistors should
be placed as close to the converter inputs as possible to the
digital ground plane (if separate grounds are used).
Ground Plane(s)
If separate digital and analog ground planes are used, then
all of the digital functions of the device and their
corresponding components should be over the digital ground
plane and terminated to the digital ground plane. The same
is true for the analog components and the analog ground
plane. The converter will function properly with a single
ground plane, as the Evaluation Board is configured in this
matter. Refer to the AppNote on the HI5760 Evaluation
Board for further discussion of the ground plane(s) upon
availability.
Noise Reduction
To minimize power supply noise, 0.1 F capacitors should be
placed as close as possible to the converter’s power supply
pins, AV
using separate digital and analog ground planes, these
capacitors should be terminated to the digital ground for
DV
of the power supplies on the board is recommended. See
the AppNote on the HI5760 Evaluation Board for more
information upon availability.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a 60 ppm /
full temperature range of the converter. It is recommended
that a 0.1 F capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO
pin (16) selects the reference. The internal reference can
be selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (to the
analog supply voltage) and the external reference driven
into REFIO, pin 17. The full scale output current of the
converter is a function of the voltage reference used and
the value of R
range, through operation below 2mA is possible, with
performance degradation.
If the internal reference is used, V
approximately 1.16V (pin 18). If an external reference is used,
V
I
I
OUT
OUT
FSADJ
DD
(Full Scale) is:
(Full Scale) = (V
and to the analog ground for AV
DD
will equal the external reference. The calculation for
and DV
SET
. I
DD
OUT
FSADJ
. Also, should the layout be designed
should be within the 2mA to 20mA
/R
15
SET
o
FSADJ
C drift coefficient over the
)x 32.
DD
will equal
. Additional filtering
HI5760
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86k R
resistor, then the input coding to output current will resemble
the following:
Outputs
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. R
chosen so that the desired output voltage is produced in
conjunction with the output full scale current, which is
described above in the ‘Reference’ section. If a known line
impedance is to be driven, then the output load resistor
should be chosen to match this impedance. The output
voltage equation is:
V
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mV
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
V
OUT
OUT
INPUT CODE (D9-D0)
HI5760
PIN 21
PIN 22
11111 11111
10000 00000
00000 00000
= 2 x I
= I
TABLE 1. INPUT CODING vs OUTPUT CURRENT
OUT
OUT
X R
IOUTA
IOUTB
x R
LOAD
EQ
.
, where R
100
FIGURE 42.
50
50
IOUTA (mA)
20
10
0
EQ
V
is ~12.5 .
OUT
LOAD
= (2 x I
50
P-P
should be
IOUTB (mA)
OUT
amplitude
SET
10
20
x R
0
EQ
)V