TDA8029C2 PHILIPS [NXP Semiconductors], TDA8029C2 Datasheet - Page 23

• Manufacturer Part Number: TDA8029C2
• Description: Low power single card reader
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Notes
1. Details on interaction with the UART behaviour in Power-down mode are described in Section 8.15.
2. Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.
8.4.2
Table 24 Interrupt priority register bits
Table 25 Description of register bits
Note
1. Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.
8.4.3
Table 26 Interrupt priority high register bits
Table 27 Description of register bits
2003 Oct 30
Symbol
Symbol
Low power single card reader
7 and 6
7 and 6
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
BIT
BIT
BIT
BIT
BIT
2
1
0
5
4
3
2
1
0
5
4
3
I
I
NTERRUPT
NTERRUPT
EX1
ET0
EX0
PT2
PS
PT1
PX1
PT0
PX0
PT2H
PSH
PT1H
SYMBOL
SYMBOL
SYMBOL
P
P
7
7
RIORITY
RIORITY
(IP)
H
External interrupt 1 enable. EX1 = 1 enables the interrupt; EX1 = 0 disables the
interrupt.
Timer 0 interrupt enable. ET0 = 1 enables the interrupt; ET0 = 0 disables the interrupt.
External interrupt 0 enable. EX0 = 1 enables the interrupt; EX0 = 0 disables the
interrupt.
Not implemented. Reserved for future use; note 1.
Timer 2 interrupt priority. See Table 20.
Serial port interrupt priority. See Table 20.
Timer 1 interrupt priority. See Table 20.
External interrupt 1 priority. See Table 20.
Timer 0 interrupt priority. See Table 20.
External interrupt 0 priority. See Table 20.
Not implemented. Reserved for future use; note 1.
Timer 2 interrupt priority. See Table 20.
Serial port interrupt priority. See Table 20.
Timer 1 interrupt priority. See Table 20.
IGH
REGISTER
6
6
(IPH)
REGISTER
PT2H
PT2
5
5
23
PSH
PS
4
4
DESCRIPTION
DESCRIPTION
DESCRIPTION
PT1H
PT1
3
3
(1)
PX1H
PX1
2
2
PT0H
PT0
Product specification
1
1
TDA8029
PX0H
PX0
0
0