AD9287BCPZRL-100 AD [Analog Devices], AD9287BCPZRL-100 Datasheet - Page 19

• Manufacturer Part Number: AD9287BCPZRL-100
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: AD [Analog Devices]

For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates the positive and negative reference voltages, REFT
and REFB, respectively, that define the span of the ADC core.
The output common-mode of the reference buffer is set to
midsupply, and the REFT and REFB voltages and span are
defined as
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is always achieved by setting the
ADC to the largest span in a differential configuration. In the
case of the AD9287, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways in which to drive the AD9287 either
actively or passively. In either case, the optimum performance is
achieved by driving the analog input differentially. One example
is by using the AD8332 differential driver. It provides excellent
performance and a flexible interface to the ADC (see Figure 41)
for baseband applications. This configuration is common for
medical ultrasound systems.
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9287. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. Two
examples are shown in Figure 38 and Figure 39.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
1V p-p
0.1μF
120nH
0.1μF
22pF
18nF
INH
LMD
Figure 41. Differential Input Configuration Using the AD8332
274Ω
LNA
LOP
LON
AD8332
0.1μF
0.1μF
Rev. 0 | Page 19 of 52
VIP
VIN
VGA
VOH
VOL
2V p-p
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+
pin while the VIN− pin is terminated. Figure 40 details a typical
single-ended input configuration.
Figure 39. Differential Transformer Coupled Configuration for IF Applications
2V p-p
2V p-p
187Ω
187Ω
65Ω
1
374Ω
16nH
C
Figure 38. Differential Transformer Coupled Configuration
1
1kΩ
1kΩ
C
DIFF
DIFF
49.9Ω
AVDD
49.9Ω
IS OPTIONAL
0.1μF
0.1μF
0.1μF
IS OPTIONAL
1kΩ
1kΩ
Figure 40. Single-Ended Input Configuration
1.0kΩ
1.0kΩ
0.1µF
0.1μF
AVDD
ADT1–1WT
1:1 Z RATIO
ADT1–1WT
1:1 Z RATIO
AVDD
0.1µF
for Baseband Applications
0.1μF
1kΩ 25Ω
1kΩ
R
R
C
0.1μF
1kΩ
499Ω
10μF
AVDD
16nH
16nH
1
1
R
R
C
C
DIFF
DIFF
R
2.2pF
33Ω
33Ω
R
AD9287
C
C
C
C
VIN–
ADC
VIN+
1kΩ
VREF
VIN+
VIN–
VIN–
VIN+
AD9287
AD9287
ADC
ADC
AGND
VIN+
VIN–
AD9287
AD9287
ADC