AD9874BST AD [Analog Devices], AD9874BST Datasheet - Page 28

• Manufacturer Part Number: AD9874BST
• Description: IF Digitizing Subsystem
• Manufacturer: AD [Analog Devices]

AD9874
Referring to Figure 18, the gain of the VGA is set by an 8-bit
control DAC that provides a control signal to the VGA appearing
at the gain control pin (GCP). For applications implementing
automatic gain control, the DAC’s output resistance can be
reduced by a factor of 9 to decrease the attack time of the AGC
response for faster signal acquisition. An external capacitor,
C
DAC’s output each time it updates as well as to filter wideband
noise. Note, C
output resistance, sets the –3 dB bandwidth and time constant
associated with this RC network.
A linear estimate of the received signal strength is performed at
the output of the first decimation stage (DEC1) and output of
the DVGA (if enabled) as discussed in the AGC section. This
data is available as a 6-bit RSSI field within an SSI frame with
60 corresponding to a full-scale signal for a given AGC attenua-
tion setting. The RSSI field is updated at f
with the 8-bit attenuation field (or AGCG attenuation setting)
to determine the absolute signal strength.
The accuracy of the mean RSSI reading (relative to the IF input
power) depends on the input signal’s frequency offset relative to
the IF frequency since both DEC1 filter’s response as well as the
ADC’s signal transfer function attenuates the mixer’s downconverted
signal level centered at f
strength of input signals falling within proximity to the IF is
reported accurately, while those signals at increasingly higher
frequency offsets incur larger measurement errors. Figure 20 shows
the normalized error of the RSSI reading as a function of the
frequency offset from the IF frequency. Note, the significance of
this error becomes apparent when determining the maximum
input interferer (or blocker) levels with the AGC enabled.
Automatic Gain Control (AGC)
The gain of the VGA (and DVGA) is automatically adjusted
when the AGC is enabled via the AGCR field of Register 0x06.
In this mode, the gain of the VGA is continuously updated at
f
level into the ADC does not exceed the ADC clip level and that
the rms output level of the ADC is equal to a programmable
reference level. With the DVGA enabled, the AGC control loop
also attempts to minimize the effects of 16-bit truncation noise
prior to the SSI output by continuously adjusting the DVGA’s
CLK
DAC
Figure 20. Normalized RSSI Error vs. Normalized IF
Frequency Offset
/60 in an attempt to ensure that the maximum analog signal
, from GCP to analog ground is required to “smooth” the
–12
–15
–18
–3
–6
–9
0
0
DAC
NORMALIZED FREQUENCY OFFSET – (
, in combination with the DAC’s programmable
0.01
CLK
/8. As a result, the estimated signal
0.02
0.03
CLK
f
/60 and can be used
IN
–
0.04
f
IF
)
f
CLK
0.05
–28–
gain to ensure maximum digital gain while not exceeding the
programmable reference level.
This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB,
and 15 dB below the ADC saturation (clip) level by writing
values from 1 to 5 to the 3-bit AGCR field. Note, the ADC clip
level is defined to be 2 dB below its full scale (i.e., –18 dBm at
the LNA input for a matched input and maximum attenuation).
If AGCR is 0, automatic gain control is disabled. Since clipping
of the ADC input will degrade the SNR performance, the refer-
ence level should also take into consideration the peak-to-rms
characteristics of the target (or interferer) signals.
Referring again to Figure 18, the majority of the AGC loop operates
in the discrete time domain. The sample rate of the loop is f
therefore, registers associated with the AGC algorithm are updated
at this rate. The number of overload and ADC reset occurrences
within the final I/Q update rate of the AD9874, as well as the
AGC value (8 MSBs), can be read from the SSI data upon proper
configuration.
The AGC performs digital signal estimation at the output of the
first decimation stage (DEC1) as well as the DVGA output that
follows the last decimation stage (DEC3). The rms power of the
I and Q signal is estimated by the following equation:
Signal estimation after the first decimation stage allows the AGC
to cope with out-of-band interferers and in-band signals that
could otherwise overload the ADC. Signal estimation after the
DVGA allows the AGC to minimize the effects of the 16-bit
truncation noise.
When the estimated signal level falls within the range of the AGC,
the AGC loop adjusts the VGA (or DVGA) attenuation setting
so that the estimated signal level is equal to the programmed level
specified in the AGCR field. The absolute signal strength can be
determined from the contents of the ATTN and RSSI field that is
available in the SSI data frame when properly configured. Within
this AGC tracking range, the 6-bit value in the RSSI field remains
constant while the 8-bit ATTN field varies according to the
VGA/DVGA setting. Note, the ATTN value is based on the 8 MSBs
contained in the AGCG field of Registers 0x03 and 0x04.
A description of the AGC control algorithm and the user adjust-
able parameters follows. First, consider the case in which the
in-band target signal is bigger than all out-of-band interferers
and the DVGA is disabled. With the DVGA disabled, a control
loop based only on the target signal power measured after DEC1
is used to control the VGA gain, and the target signal will be
tracked to the programmed reference level. If the signal is too large,
the attenuation is increased with a proportionality constant
determined by the AGCA setting. Large AGCA values result in
large gain changes, thus rapid tracking of changes in signal
strength. If the target signal is too small relative to the reference
level, the attenuation is reduced; but now the proportionality
constant is determined by both the AGCA and AGCD settings.
The AGCD value is effectively subtracted from AGCA, so a
large AGCD results in smaller gain changes and thus slower
tracking of fading signals.
The 4-bit code in the AGCA field sets the raw bandwidth of the
AGC loop. With AGCA = 0, the AGC loop bandwidth is at its
minimum of 50 Hz assuming f
of AGCA increases the loop bandwidth by a factor of 2
Xest n
[ ]
=
Abs I n
( )
[ ]
+
Abs Q n
(
CLK
[ ]
= 18 MHz. Each increment
)
1/2
REV. 0
CLK
, thus
/60;
(7)