AD9874BST AD [Analog Devices], AD9874BST Datasheet - Page 18

• Manufacturer Part Number: AD9874BST
• Description: IF Digitizing Subsystem
• Manufacturer: AD [Analog Devices]

AD9874
As shown in Figure 4b, AD9874’s synchronous serial interface
(SSI) links the receive data stream to the DSP’s Serial Port (SPORT).
For AD9874 set-up and register programming, the device connects
directly to ADSP-2153x’s SPI-PORT. Dedicated select lines (SEL)
allow the ADSP-2153x to program and read back registers of
multiple devices using only one SPI port. The DSP driver code
pertaining to this interface is available on the AD9874 web page
(http://products.analog.com/products/info.asp?product=AD9874).
POWER CONTROL
To allow power consumption to be minimized, the AD9874
possesses numerous SPI-programmable power-down and bias
control bits. The AD9874 powers up with all of its functional
blocks placed into a standby state (i.e., STBY Register default is
0xFF). Each major block may then be powered up by writing a 0
to the appropriate bit of the STBY Register. This scheme provides
the greatest flexibility for configuring the IC to a specific appli-
cation as well as for tailoring the IC’s power-down and wake-up
characteristics. Table VI summarizes the function of each of the
STBY bits. Note, when all the blocks are in standby, the master
reference circuit is also put into standby and thus the current is
reduced by a further 0.4 mA.
STBY
Bit
7:REF
6:LO
5:CKO
4:CK
3:GC
2:LNAMX LNA and Mixer OFF. CXVM,
1:Unused
0:ADC
NOTES
1
2
Figure 4b. Example of AD9874 and ADSP-2153x Interface
Wake-up time is dependent on programming and/or external components.
When all blocks are in standby, the master reference circuit is also put into
standby and thus the current is reduced by a further 0.4 mA.
Effect
Voltage Reference OFF;
all biasing shut down.
LO Synthesizer OFF,
IOUTL three-state.
Clock Oscillator OFF
Clock Synthesizer OFF,
IOUTC three-state. Clock
buffer OFF if ADC is OFF.
Gain Control DAC OFF.
GCP and GCN three-state.
CXVL, and CXIF three-state.
ADC OFF; Clock Buffer OFF
if CLK synthesizer OFF; VCM
three-state; Clock to the digital
filter halted; Digital outputs
static.
SPI
SSI
Table VI. Standby Control Bits
AD9874
CLKOUT
DOUTB
DOUTA
PC
PD
PE
FS
SCK
SEL
MOSI
MISO
RSCLK
RFS
DR
ADSP-2153X
Current
Reduction Wake-Up
(mA)
0.6
1.2
1.1
1.3
0.2
8.2
9.2
SPI-PORT
SERIAL
PORT
1
Time (ms)
<0.1 (C
= 4.7 nF)
Note 2
Note 2
Note 2
Depends
on C
<2.2
<0.1
GC
REF
–18–
The AD9874 also allows control over the bias current in the LNA,
mixer, and clock oscillator. The effects on current consumption
and system performance are described in the section dealing
with the affected block.
LO Synthesizer
The LO Synthesizer shown in Figure 5 is a fully programmable
PLL capable of 6.25 kHz resolution at input frequencies up to
300 MHz and reference clocks of up to 25 MHz. It consists of a
low noise digital phase-frequency detector (PFD), a variable
output current charge pump (CP), a 14-bit reference divider,
programmable A and B counters, and a dual-modulus 8/9 prescaler.
The A (3-bit) and B (13-bit) counters, in conjunction with the
dual 8/9 modulus prescaler, implement an N divider with N =
8
allows selectable input reference frequencies, f
input. A complete PLL (phase-locked loop) can be implemented
if the synthesizer is used with an external loop filter and VCO
(voltage controlled oscillator).
The A, B, and R counters can be programmed via the following
registers: LOA, LOB, and LOR. The charge pump output current
is programmable via the LOI Register from 0.625 mA to 5.0 mA
using the following equation:
An on-chip fast acquire function (enabled by the LOF bit)
automatically increases the output current for faster settling
during channel changes. The synthesizer may also be disabled
using the LO standby bit located in the STBY Register.
f
The LO (and CLK) synthesizer works in the following manner.
The externally supplied reference frequency, f
divided by the value held in the R counter. The internal f
then compared to a divided version of the VCO frequency, f
The phase/frequency detector provides UP and DOWN pulses
whose widths vary depending upon the difference in phase and
frequency of its two input signals. The UP/DOWN pulses con-
trol the charge pump making current available to charge the
external low-pass loop filter when there is a discrepancy between
the inputs of the PFD. The output of the low-pass filter feeds an
external VCO whose output frequency, f
its divided down version, f
the feedback loop.
The synthesized frequency is related to the reference frequency
and the LO Register contents as follows:
Note, the minimum allowable value in the LOB Register is 3 and
its value must always be greater than that loaded into LOA.
REF
IPUMP
f
B + A. In addition, the 14-bit reference counter (R Counter)
LO
BUFFER
=
REF
(
8
=
×
(
LOB
LOI
Figure 5. LO Synthesizer
LOR
+
LOA, LOB
+
R
1
COUNTERS
LOA
)
F
×
REF
A, B
0 625
LO
.
) /
, matches that of f
FREQUENCY
DETECTOR
LOR
F
PHASE/
LO
mA
×
8/9
f
REF
LO
, is driven such that
REF
REF
ACQUIRE
REF
BUFFER
CHARGE
FAST
, is buffered and
PUMP
, at the PFD
LO
, thus closing
TO EXTERNAL
REV. 0
FILTER
LOOP
REF
f
FROM
VCO
LO
LO
(2)
(3)
is
.