74LVT573 PHILIPS [NXP Semiconductors], 74LVT573 Datasheet - Page 2

• Manufacturer Part Number: 74LVT573
• Description: 3.3V Octal D-type transparent latch 3-State
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
20-Pin Plastic SOL
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
1998 Feb 19
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
3-State output buffers
Common output enable
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
Power-up 3-State
Power-up reset
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
3.3V Octal D-type transparent latch
(3-State)
SYMBOL
C
t
t
I
C
CCZ
PLH
PHL
OUT
IN
PACKAGES
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
10
1
2
3
4
5
6
7
8
9
PARAMETER
SV00031
TEMPERATURE RANGE
20
19
18
17
16
15
14
13
12
11
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
CC
C
V
Outputs disabled; V
Outputs disabled; V
I
L
OUTSIDE NORTH AMERICA
= 0V or 3.0V
= 50pF; V
2
T
DESCRIPTION
The LVT573 is a high-performance BiCMOS product designed for
VCC operation at 3.3V. This device is an octal transparent latch
coupled to eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (E) and Output
Enable (OE) control gates. The 74LVT573 has a broadside pinout
configuration to facilitate PC board layout and allow easy interface
with microprocessors.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
When OE is Low, the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
PIN DESCRIPTION
74LVT573 PW
74LVT573 DB
amb
74LVT573 D
2, 3, 4, 5, 6, 7, 8, 9
19, 18, 17, 16, 15,
CC
PIN NUMBER
CONDITIONS
= 25 C; GND = 0V
14, 13, 12
= 3.3V
O
CC
11
10
20
1
= 0V or 3.0V
= 3.6V
SYMBOL
NORTH AMERICA
74LVT573PW DH
Q0-Q7
D0-D7
GND
74LVT573 DB
V
OE
74LVT573 D
E
CC
TYPICAL
Output enable input
(active-Low)
Data inputs
Data outputs
Enable input
(active-High)
Ground (0V)
Positive supply voltage
2.5
2.7
.13
4
8
Product specification
74LVT573
FUNCTION
DWG NUMBER
853–1750 18988
SOT163-1
SOT339-1
SOT360-1
UNIT
mA
ns
pF
pF