ISL5216_05 INTERSIL [Intersil Corporation], ISL5216_05 Datasheet - Page 45

• Manufacturer Part Number: ISL5216_05
• Description: Four-Channel Programmable Digital DownConverter
• Manufacturer: INTERSIL [Intersil Corporation]

P(15:0)
P(31:0)
20:18
15:13
2:0
24
23
22
21
17
16
12
11
10
5
4
3
When set to 1, this bit will keep the serial clock disabled after a hardware reset until receipt of the first SYNCI signal.
Enables resetting serial clock divider on SYNCI. When enabled, a SYNCI enabled for any of the four serial data outputs in the
Reset/Sync register (GWA = F802h, bits 24, 16, 8 or 0) will reset the serial clock divider.
SCLK polarity.
1
0
SCLK rate.
000
001
010
011
100
101
Other codes are undefined.
Set to 0.
Set to 0.
Set to 0.
Not used. Set to zero.
Input level detector floating point saturation level. Offsets the exponent to normalize the shift code. The ones-complement of these
bits is added to the exponent bits from the input section to obtain the shift code, allowing the user to normalize the inputs to the same
bit weights in the accumulators. For example, if the maximum expected exponent is 5 (101), programming this value into 20:18
causes 2 (010) to be added to the exponent normalizing it to a full scale shift code of 7. Set to 000 for fixed point inputs.
Enables the new (ISL5216) floating point modes; the 11-, 12-, 13- and 14-bit modes with 42dB of gain, and 15- and 16-bit modes
with 18dB and 6dB ranges, respectively. The X-1 input must be used for 14-, 15- and 16-bit modes. See Floating Point Input Mode
Bit Mapping Tables for details.
Floating point mode select bit 2. Used with GWA F804h, bits 8:7 to select the floating point mode/format. See Floating Point Input
Mode Bit Mapping Tables for details.
Channel Input Source Selection. Selects as the data input for the level detector either A(15:0), B(15:0), C(15:0), D(15:0) or the µP
Test Input register as shown below.
15:13
000
001
010
011
100
µP Register input enable select
1 = bit 11, 0 = one clock wide pulse on each write to location F808h. Select 0 to write data test data into the part. Select 1 to input a
constant or to disable the input for minimum power dissipation when the input level detector section is unused.
µP input enable. When bit 12 is set, this bit is the input enable for the µP register input. Active low. 0=enabled, 1=disabled.
Parallel Data Input Format
0
1
Clock low to high transition occurs at the center of the data bit.
Clock high to low transition at the center of the data bit.
Two’s complement
Offset binary
Serial clock disabled.
Serial clock rate is Input CLK Rate.
Serial clock rate is Input CLK Rate/2.
Serial clock rate is Input CLK Rate/4.
Serial clock rate is Input CLK Rate/8.
Serial clock rate is Input CLK Rate/16.
Source Selected
A(15:0)
B(15:0)
C(15:0)
D(15:0)
µP Test input register.
This is provided for testing and to zero the input data bus when a channel is not in use.
The Global Write Address register for the µP Test input register is F807h.
TABLE 41. INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h)
45
TABLE 40. SERIAL CLOCK CONTROL REGISTER (GWA = F803h)
ISL5216
FUNCTION
FUNCTION
July 8, 2005