ISL5216_05 INTERSIL [Intersil Corporation], ISL5216_05 Datasheet - Page 27

• Manufacturer Part Number: ISL5216_05
• Description: Four-Channel Programmable Digital DownConverter
• Manufacturer: INTERSIL [Intersil Corporation]

Table 1 details the phase and magnitude weighting for the 16
bits output from the PDC.
23 (MSB)
0 (LSB)
BIT
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TABLE 1. MAG/PHASE BIT WEIGHTING
MAGNITUDE
2
2
2
2
2
2
2
2
2
2
2
2
27
2
2
2
2
2
2
2
2
2
2
2
2
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-1
-2
-3
-4
-5
-6
-7
-8
-9
2
1
0
180
90
45
22.5
11.25
5.625
2.8125
1.40625
0.703125
0.3515625
0.17578125
0.087890625
0.043945312
0.021972656
0.010986328
0.005483164
0.002741582
0.001370791
0.0006853955
0.00034269775
0.00017134887
0.00008567444
0.00004283722
0.00002141861
PHASE (
o
)
ISL5216
The magnitude and phase computation requires 17 clocks
for full precision. At the end of the 17 clocks, the magnitude
and phase are latched into a register to be held for the next
stage, either the output formatter or frequency discriminator.
If a new input sample arrives before the end of the 17 cycles,
the results of the computations up until that time, are
latched. This latching means that an increase in speed
causes only a decrease in accuracy. Table 2 details the exact
accuracy that can be obtained with a fixed number of clock
cycles up to the maximum of 17. The input magnitude and
phase errors induced by normal SNR values will almost
always be worse than the Cartesian to Polar conversion.
†
Assumes ±180
CLOCKS
TABLE 2. MAG/PHASE ACCURACY vs CLOCK CYCLES
10
11
12
13
14
15
16
17
6
7
8
9
o
MAGNITUDE
= f
ERROR
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
(% f
S
0.065
0.016
0.004
.
S
)
PHASE ER-
(DEG.)
0.00175
0.0035
0.056
0.028
0.014
0.007
ROR
0.45
0.22
0.11
3.5
1.8
0.9
†
PHASE ER-
(% f
0.062
0.016
0.008
0.004
0.002
0.001
ROR
0.25
0.12
0.03
0.5
July 8, 2005
2
1
S
)