74LVC74A PHILIPS [NXP Semiconductors], 74LVC74A Datasheet - Page 2

• Manufacturer Part Number: 74LVC74A
• Description: Dual D-type flip-flop with set and reset; positive-edge trigger
• Manufacturer: PHILIPS [NXP Semiconductors]

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
PIN CONFIGURATION
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
1998 Jun 17
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A.
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50 W transmission lines @ 85 C
Dual D-type flip-flop with set and reset;
positive-edge trigger
P
f
f
i
o
PD
D
= input frequency in MHz; C
= output frequency in MHz; V
(C
= C
is used to determine the dynamic power dissipation (P
L
SYMBOL
t
PHL/
PD
f
C
V
max
C
PACKAGES
CC
PD
amb
t
I
PLH
V
2
CC
= 25 C; t
GND
1CP
1R
1S
f
1Q
1Q
1D
2
o
D
) = sum of the outputs.
D
I
= GND to V
f
i
1
2
3
4
5
6
7
) (C
r
= t
Propagation delay
nCP to nQ, nQ
nS
nR
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
f
D
D
L
L
2.5 ns
to nQ, nQ
to nQ, nQ
CC.
= output load capacity in pF;
CC
V
CC
= supply voltage in V;
SV00491
2
TEMPERATURE RANGE
14
13
12
10
11
9
8
f
o
V
2R
2D
2CP
2S
2Q
2Q
PARAMETER
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
) + (V
CC
D
D
O
2
/R
L
)
D
duty factor LOW, where:
in W)
OUTSIDE NORTH AMERICA
2
C
V
Notes 1 and 2
DESCRIPTION
The 74LVC74A is a high-performance, low-voltage Si-gate CMOS
device and superior to most advanced CMOS compatible TTL
families.
The 74LVC74A is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in all data inputs makes the circuit highly
tolerant to slower clock rise and fall times.
74LVC74A PW
LOGIC SYMBOL (IEEE/IEC)
74LVC74A DB
CC
74LVC74A D
L
= 50 pF;
CONDITIONS
= 3.3 V
10
11
12
13
4
3
2
1
NORTH AMERICA
74LVC74APW DH
1D
R
2D
R
S
S
C1
C2
74LVC74A DB
74LVC74A D
TYPICAL
250
3.6
3.5
3.5
5.0
30
SV00332
Product Specification
74LVC74A
DWG NUMBER
5
6
9
8
D
853-2070 19589
) and (R
SOT108-1
SOT337-1
SOT402-1
UNIT
MHz
pF
pF
ns
D
)