M48T35-70MH1 STMICROELECTRONICS [STMicroelectronics], M48T35-70MH1 Datasheet - Page 4

• Manufacturer Part Number: M48T35-70MH1
• Description: 256 Kbit 32Kb x8 TIMEKEEPER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48T35, M48T35Y
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year), 30, and 31
day months are made automatically. Byte 7FF8h
is the clock control register. This byte controls user
access to the clock information and also stores the
clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T35/35Y includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
The M48T35/35Y also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
below approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
READ MODE
The M48T35/35Y is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
4/18
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
AVQV
) after the last address input signal is
CC
is out of tolerance, the circuit
CC
. As V
0 to 3V
1.5V
5ns
CC
falls
Figure 4. AC Testing Load Circuit
Access time (t
(t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (t
nate until the next Address Access.
WRITE MODE
The M48T35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
able prior to the initiation of another read or write
cycle. Data-in must be valid t
of write and remain valid for t
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs t
GLQV
EHAX
C L includes JIG capacitance
DEVICE
UNDER
).
TEST
from Chip Enable or t
AVQV
ELQV
, the data lines will be driven to an
1k
) or Output Enable Access time
AXQX
WLQZ
AVQV
) but will go indetermi-
5V
DVWH
WHAX
after W falls.
.
WHDX
1.9k
C L = 100pF or 5pF
prior to the end
from Write En-
afterward. G
OUT
AI01030