M41TTHSMH6E STMICROELECTRONICS [STMicroelectronics], M41TTHSMH6E Datasheet
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M41TTHSMH6E
Related parts for M41TTHSMH6E
M41TTHSMH6E Summary of contents
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Serial Real Time Clock with 44Bytes NVRAM and Reset Feature summary Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32KHz crystal oscillator integrating load capacitance (12.5pF) providing exceptional oscillator stability and high crystal series ...
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Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41T94 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41T94 List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary description 1 Summary description The M41T94 is a Serial Real Time Clock with 44 bytes of NVRAM and a RESET output. A built-in 32,768Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 4 on page ...
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M41T94 Figure 1. Logic diagram 1. For SO16 package only. Figure 2. 16-pin SOIC connections ( BAT (1) XI (1) XO SCL SDI M41T94 E RSTIN1 RSTIN2 WDI THS ...
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Summary description Table 1. Signal names E IRQ/FT/OUT RST RSTIN1 RSTIN2 SCL SDI SDO SQW THS WDI (1) XI (1) XO (1) V BAT For SO16 package only. Figure 3. 28-pin SOIC connections 8/40 Chip ...
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M41T94 Figure 4. Block diagram E SDO SDI INTERFACE SCL 32KHz Crystal OSCILLATOR WDI BAT RSTIN1 RSTIN2 1. Open drain output Figure 5. Hardware hookup SPI Interface with (CPOL, CPHA) (1) = ('0','0') or ('1','1') Master (ST6, ...
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Summary description Table 2. Function table Mode Disable reset WRITE READ 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ. Figure 6. Data and clock timing CPOL CPHA 0 ...
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M41T94 2 Signal description 2.1 Serial data output (SDO) The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. 2.2 Serial data input (SDI) The ...
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Operation 3 Operation The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL, SDI and SDO (see ...
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M41T94 3.1 SPI bus characteristics The Serial Peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: Serial data input (SDI), Serial data output (SDO), Serial clock (SCL) and a Chip Enable ...
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Operation Figure 8. Output timing requirements E SCL tCLQV tCLQX MSB OUT SDO ADDR. LSB IN SDI 14/40 tCH tCL LSB OUT tQLQH tQHQL M41T94 tEHQZ AI04634 ...
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M41T94 Table 3. AC characteristics Symbol f Serial clock input frequency SCL (2) t Clock high CH (3) t Clock transition (fall time) CHCL t Serial clock input high to input data transition CHDX t Serial clock input high to ...
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Operation 3.2 READ and WRITE cycles Address and data are shifted MSB first into the Serial Data Input (SDI) and out of the Serial Data Output (SDO). Any data transfer considers the first bit to define whether a READ or ...
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M41T94 Figure 9. READ mode sequence SCL 7 BIT ADDRESS W/R BIT SDI MSB SDO HIGH IMPEDANCE Figure 10. WRITE mode sequence SCL 7 BIT ADDR ...
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Clock operations 4 Clock operations The eight byte clock register (see read the date and time from the clock binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Bits ...
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M41T94 Table 4. Clock register map Addr D7 00h 01h ST 02h 0 03h CEB 04h TR 05h 0 06h 0 07h 08h OUT 09h WDS BMB4 BMB3 0Ah AFE SQWE 0Bh RPT4 RPT5 0Ch RPT3 0Dh RPT2 0Eh RPT1 ...
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Clock operations 4.3 Setting Alarm clock registers Address locations 0Ah-0Eh contain the Alarm settings. The Alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, ...
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M41T94 Figure 11. Alarm interrupt reset Waveforms 0Eh ACTIVE FLAG IRQ/FT/OUT Figure 12. Back-up mode Alarm Waveforms PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT 0Fh HIGH-Z Clock operations 10h ...
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Clock operations 4.4 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog register, address 09h. bits BMB4-BMB0 store a binary ...
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M41T94 Table 6. Square Wave output frequency RS3 4.6 Power-on reset The M41T94 continuously monitors V the RST pulls low (open drain) and remains ...
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Clock operations Figure 13. RSTIN1 and RSTIN2 timing Waveforms RSTIN1 RSTIN2 (1) RST Table 7. Reset AC characteristics Symbol (2) t RLRH1 (3) t RLRH2 (4) t R1HRH (4) t R2HRH 1. Valid for ambient operating temperature Pulse ...
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M41T94 adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total ...
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Clock operations Figure 14. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 Figure 15. Calibration Waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 4.9 Century bit Bits D7 and D6 of clock ...
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M41T94 4.10 Output driver pin When the FT bit, AFE bit and Watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents the Control register. In other words, when D7 (OUT ...
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Clock operations 4.13 Initial power-on defaults Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' ...
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M41T94 5 Maximum rating Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
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DC and AC parameters 6 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived ...
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M41T94 Table 13. DC characteristics Symb. Battery current OSC on I BAT Battery current OSC off I Supply current CC1 I Supply current (standby) CC2 (2) I Input leakage current LI (3) I Output leakage current LO V Input high ...
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DC and AC parameters Figure 17. Power down/up mode AC Waveforms PFD (max) V PFD (min INPUTS RST OUTPUTS (PER CONTROL INPUT) Table 15. Power Down/Up AC Characteristics Symbol ( (max ...
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M41T94 7 Package mechanical information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on ...
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Package mechanical information Figure 18. SO16 – 16-lead plastic small outline package outline 1. Drawing is not to scale. Table 16. SO16 – 16-lead Plastic small outline package mechanical data Symbol ...
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M41T94 Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline 1. Drawing is not to scale. Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package mechanical data Symbol ...
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Package mechanical information Figure 20. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline 1. Drawing is not to scale. Table 18. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data Symbol A ...
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M41T94 Figure 21. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline 1. Drawing is not to scale. Table 19. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data Symbol ...
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Part numbering 8 Part numbering Table 20. Ordering information scheme Example: Device type M41T Supply voltage and write protect voltage 2.7 to 5.5V CC THS = V ; 4.20V V CC THS = V ; 2.55V ...
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M41T94 9 Revision history Table 22. Document Revision History Date Version April 2002 25-Apr-02 03-Jul-02 06-Nov-02 26-Mar-03 28-Apr-03 15-Jun-04 29-Aug-2006 1.0 First edition Adjust graphic (Figure 4 on page 1.1 Table 20 on page 38); adjust characteristics Table 14 on ...
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...