M41T93_11 STMICROELECTRONICS [STMicroelectronics], M41T93_11 Datasheet - Page 24
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M41T93_11
Manufacturer Part Number
M41T93_11
Description
Serial SPI bus real-time clock with battery switchover
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M41T93_11.pdf
(51 pages)
Clock operation
3.4.2
24/51
Analog calibration (programmable load capacitance)
A second method of calibration employs the use of programmable internal load capacitors to
adjust (or trim) the oscillator frequency.
By design, the oscillator is intended to be 0 ppm ± crystal accuracy at room temperature
(25 °C, see
the crystal will be 25 pF. For incrementing or decrementing the calibration value,
capacitance will be added or removed in increments of 0.25 pF to each side of the crystal.
Internally, C
C
effective on-chip series load capacitance, C
nominal value of 12.5 pF (AC0-AC6 = ‘0’).
The effective series load capacitance (C
Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load
capacitance value for frequency compensation of the RTC. Each bit has a different weight
for capacitance adjustment. An analog calibration sign (ACS) bit determines if capacitance
is added (ACS bit = ‘0,’ negative calibration) or removed (ACS bit = ‘1,’ positive calibration).
The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency
by removing capacitance) due to the typical characteristic of quartz crystals to slow down
due to changes in temperature, but negative calibration is also available.
Since the analog calibration register adjustment is essentially “pulling” the frequency of the
oscillator, the resulting frequency changes will not be linear with incremental capacitance
changes. The equations which govern this mechanism indicate that smaller capacitor values
of analog calibration adjustment will provide larger increments. Thus, the larger values of
analog calibration adjustment will produce smaller incremental frequency changes. These
values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest
capacitance settings. The range provided by the analog calibration register adjustment with
a typical surface mount crystal is approximately ±30 ppm around the AC6-AC0 = 0 default
setting because of this property (see
XO
, connected from the XI and XO pins to ground (see
Figure 11 on page
LOAD
of the oscillator is changed via two digitally controlled capacitors, C
Doc ID 12615 Rev 6
C
25). For a 12.5 pF crystal, the default loading on each side of
LOAD
Table 5 on page
=
LOAD
1
LOAD
1 C
) is the combination of C
, ranges from 3.5 pF to 17.4 pF, with a
XI
+
1 C
25).
Figure 10 on page
XO
XI
and C
21). The
XO
:
M41T93
XI
and