CDP68HC68T1W INTERSIL [Intersil Corporation], CDP68HC68T1W Datasheet - Page 12

• Manufacturer Part Number: CDP68HC68T1W
• Description: CMOS Serial Real-Time Clock With RAM and Power Sense/Control
• Manufacturer: INTERSIL [Intersil Corporation]

STATUS REGISTER (Read Only) - Address 30H
NOTES:
10. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE
WATCHDOG
If this bit is set high, the watchdog circuit has detected a
CPU failure.
TEST MODE
When this bit is set high, the device is in the TEST MODE.
FIRST-TIME UP
Power-on reset sets this bit high. This signifies that data in
the RAM and Clock is not valid and should be initialized.
INTERRUPT TRUE
A high in this bit signifies that one of the three interrupts
(Power Sense, Alarm, and Clock) is valid.
POWER-SENSE INTERRUPT
This bit set high signifies that the power-sense circuit has
generated an interrupt.
ALARM INTERRUPT
When the seconds, minutes and hours time and alarm
counter are equal, this bit will be set high. Status Register
must be read before loading Interrupt Control Register for
valid alarm indication after alarm activates.
CLOCK INTERRUPT
A periodic interrupt will set this bit high.
All bits are reset by a power-on reset except the “FIRST-
TIME UP” which is set. All bits except the power-sense bit
are reset after a read of this register.
9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register.
cycle.
D7
0
DISABLE
RESET
WRITE
MODE
READ
WATCHDOG
D6
MODE
CE
TEST
H
H
L
D5
FIRST
CDP68HC68T1
TIME
D4
UP
INPUT DISABLED
TRUTH TABLE
SCK (Note 9)
CPOL = 1
CPOL = 0
CPOL = 1
CPOL = 0
12
Pin Signal Description
SCK (Serial Clock Input, Note 11)
This input causes serial data to be latched from the MOSI
input and shifted out on the MISO output.
MOSI (Master Out/Slave In, Note 11)
Data bytes are shifted in at this pin, most significant bit
(MSB) first.
MISO (Master In/Slave Out)
Data bytes are shifted out at this pin, most significant bit
(MSB) first.
CE (Chip Enable, Note 12)
A positive chip-enable input. A low level at this input holds
the serial interface logic in a reset state, and disables the
output driver at the MISO pin.
NOTES:
11. These inputs will retain their previous state if the line driving
12. The CE input has as internal pull down device, if the input is in a
Functional Description
The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68T1 is a serial synchronous bus for address and
data transfers. The clock, which is generated by the micro-
computer is active only during address and data transfers. In
systems using the CDP68HC05C4 or CDP68HC05D2, the
INTERRUPT
TRUE
them goes into a High-Z state.
low state before going to High Z, the input can be left in a High Z.
D3
SIGNAL
INPUT DISABLED
DATA BIT LATCH
INTERRUPT
POWER
SENSE
D2
MOSI
X
INTERRUPT
ALARM
D1
NEXT DATA BIT
SHIFTED OUT
(Note 10)
HIGH Z
HIGH Z
MISO
INTERRUPT
CLOCK
D0