CDP68HC68S1M INTERSIL [Intersil Corporation], CDP68HC68S1M Datasheet - Page 6

• Manufacturer Part Number: CDP68HC68S1M
• Description: Serial Multiplexed Bus Interface
• Manufacturer: INTERSIL [Intersil Corporation]

Differential Transceiver Cell
The differential transceiver is a serial interface device which
accepts digital signals and translates this information for
transmitting on the two wire differential bus.
The transmitter section (shown in Figure 4), when transmit-
ting, provides matched constant current sources to the bus
“+” and bus “-” I/O sourcing and sinking respectively. When
transmitting, a logic zero at the “transmit data” input causes
the bus “+” I/O to provide source current and the bus “-” I/O
to provide a matched sink current. A logic one at the “trans-
mit data” input causes the bus “+” and bus “-” I/Os to simulta-
neously provide a high impedance state. The bus depends
on external resistor components for bias and termination.
Recommended resistor sizes are shown in Figure 4.
A zero transmitted on the bus will appear as a large voltage
drop across the BUS+ and BUS- pins, i.e. BUS+ might typi-
cally sit at +2.8V and BUS- at +2.2V for a logic zero. For a
logic level one, the SBlC actually three-states the BUS+ and
BUS- pins and relies on external resistors to bias the bus
lines. The lines are both biased to sit at approximately 2.5V
with a small (perhaps 20mV) voltage drop across the two
lines. In this condition the BUS- line actually sits at a slightly
higher potential than the BUS+ line. See Figure 5. Thus, the
NOTES:
DATA
RECEIVE
1. The control signal at the transmitting node.
2. The control signal at the receiving node.
3. There is a delay between the control pin being pulled low and the actual beginning of the start bit.
4. If the control pin is again puled low before the end of the stop bit, then the next start bit will begin at the end of the previous stop bit.
TRANSMIT
CONTROL (1)(3)
DIFFERENTIAL
----------------- -
BREAK
DATA
CONTROL (2)
OUTOF
RANGE
FIGURE 4. DIFFERENTIAL DRIVER/RECEIVER
XMIT
SBI CHIP
IDLE
BUS
SCK
REC
+
-
FIGURE 3. SCK, CONTROL, AND IDLE SIGNALS DURING THE SPI MODE OF OPERATION
START
BIT
V
DD
I
I
B
A
MSB
MSB
1
BUS+
BUS-
0
2
6
6
1
C
C
3
L
L
2
5
5
V
C
DD
4
L
4
4
3
13K
13K
5
3
3
4
CDP68HC68S1
120
6
2
2
DIFF.
DIFF.
5
BUS
BUS
7
6-89
1
1
6
bus actually “floats” to a logic level one, but must be driven to
a logic level zero. Logic 0-bits always dominate over logic 1-
bits on the bus. If two MCU’s simultaneously transmit a zero
and a one on the bus, the zero will override the one and the
bus will merely appear to be transmitting a zero. The “mark-
ing” or idle signal on the bus is a logic one. If the bus is idle
or if a micro is sending a logic one, then a one will appear on
the bus.
In addition to the transmission of data, the differential data
transceiver accepts at its bus “+” and bus “-” I/Os, serial dif-
ferential data which is translated into the standard digital
logic levels. This reception of data also occurs while trans-
mitting, thus reflecting the data seen on the bus back into the
SBIC data register.
The differential transceiver cell allows bus activity by other
devices on the bus “+” and bus “-” I/Os when power to the
cell is shut off. Therefore, this powered off condition places
the transceiver outputs, BUS “+” and BUS “-”, in a high
impedance state. When the cell is either being powered up
or down, with or without bus activity, SCR latch-up protection
is provided such that this activity is not affected.
VOLTAGE
APPROX.
2.8
2.5
2.2
8
LSB
LSB
7
(4)
STOP
BIT
BUS+
BUS-
IDLE IDLE
BIT BIT
1
Typical voltage levels seen on BUS+ and BUS-
I/O pins for logic zero and logic 1-bits. Notice
that the BUS- Pin is biased to actually sit a
higher voltage potential than the BUS+. Values
shown are for V
V
20mV MAX.
LOGIC 0
DD
2
= 5V
IDLE
BIT
3
IDLE
BIT
4
FIGURE 5.
IDLE
DD
BIT
5
= 5V
IDLE
BIT
6
LOGIC 0
0.6V
IDLE
BIT
7
IDLE
BIT
8
IDLE
BIT
9
IDLE
BIT
10
LOGIC 1
IDLE
BIT
11