PCF8533U PHILIPS [NXP Semiconductors], PCF8533U Datasheet - Page 18

• Manufacturer Part Number: PCF8533U
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
7
The I
between different ICs or modules. The two lines are a
Serial Data line (SDA) and a Serial Clock Line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
By connecting SDAACK to SDA on the PCF8533, the SDA
line becomes fully I
acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAACK pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8533
will not be able to create a valid logic 0 level. By splitting
the SDA input from the output the device could be used in
a mode that ignores the acknowledge bit. In COG
applications where the acknowledge cycle is required, it is
necessary to minimize the track resistance from the
SDAACK pad to the system SDA line to guarantee a valid
low level.
The following definition assumes SDA and SDAACK are
connected and refers to the pair as SDA.
7.1
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal. Bit
transfer is illustrated in Fig.10.
7.2
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P). The START
and STOP conditions are illustrated in Fig.11.
7.3
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’. The system
configuration is illustrated in Fig.12.
1999 Jul 30
Universal LCD driver for low multiplex rates
CHARACTERISTICS OF THE I
2
C-bus is for bidirectional, two-line communication
Bit transfer
START and STOP conditions
System configuration
2
C-bus compatible. Having the
2
C-BUS
18
7.4
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition. Acknowledgement on the
I
7.5
The PCF8533 acts as an I
not initiate I
master receiver. The only data output from the PCF8533
are the acknowledge signals of the selected devices.
Device selection depends on the I
on the transferred command data and on the hardware
subaddress.
In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally tied to V
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to V
accordance with a binary coding scheme such that no two
devices with a common I
same hardware subaddress.
7.6
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
2
C-bus is illustrated in Fig.13.
Acknowledge
PCF8533 I
Input filters
2
C-bus transfers or transmit data to an I
2
C-bus controller
2
C-bus slave address have the
2
C-bus slave receiver. It does
2
C-bus slave address,
Product specification
SS
PCF8533
or V
SS
which
DD
in
2
C-bus