PCF85321 NXP [NXP Semiconductors], PCF85321 Datasheet - Page 17

• Manufacturer Part Number: PCF85321
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8532_1
Product data sheet
7.12 Subaddress counter
7.13 Output bank selector
7.14 Input bank selector
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter agree with the
hardware subaddress applied to A0 and A1. The subaddress counter value is defined by
the device-select command. If the content of the subaddress counter and the hardware
subaddress do not match then data storage is inhibited but the data pointer is
incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8532 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 54th
display data byte transmitted in 1:3 multiplex mode).
The hardware subaddress must not be changed whilst the device is being accessed on
the I
The output bank selector selects one of the four bits per display RAM address for transfer
to the display register. The actual bit selected depends on the LCD drive mode in
operation and on the instant in the multiplex sequence.
The SYNC signal will reset these sequences to the following starting points:
The PCF8532 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank-select command may request the contents of
bit 2 to be selected for display instead of the contents of bit 0. In the 1:2 multiplex drive
mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode
or in bits 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The
input bank selector functions independently to the output bank selector.
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In 1:4 multiplex mode, all RAM addresses of bit 0 are selected, these are followed by
the contents of bit 1, bit 2 and then bit 3
In 1:3 multiplex mode, bits 0, 1 and 2 are selected sequentially
In 1:2 multiplex mode, bits 0 and 1 are selected
In the static mode, bit 0 is selected.
Bit 3 for 1:4 multiplex mode
Bit 2 for 1:3 multiplex mode
Bit 1 for 1:2 multiplex mode
Bit 0 for static mode
2
C-bus interface.
Rev. 1 — 10 February 2009
Universal LCD driver for low multiplex rates
PCF8532
© NXP B.V. 2009. All rights reserved.
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