PCF2129AT NXP [NXP Semiconductors], PCF2129AT Datasheet - Page 58

• Manufacturer Part Number: PCF2129AT
• Description: Integrated RTC, TCXO and quartz crystal
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 55.
All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %
and 70 % with an input voltage swing of V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
PCF2129A_1
Product data sheet
Symbol Parameter
Pin SCL
f
t
t
Pin SDA
t
t
Pins SCL and SDA
t
t
t
t
t
t
t
t
t
SCL
LOW
HIGH
SU;DAT
HD;DAT
BUF
SU;STO
HD;STA
SU;STA
r
f
VD;ACK
VD;DAT
SP
The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is
held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of the SCL’s falling edge.
C
series protection resistors to be connected between the SDA pin, the SCL pin, and the SDA/SCL bus lines without exceeding the
maximum t
t
t
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
The maximum t
VD;ACK
VD;DAT
b
is the total capacitance of one bus line in pF.
SCL clock frequency
LOW period of the SCL
clock
HIGH period of the SCL
clock
data set-up time
data hold time
bus free time between a
STOP and START
condition
set-up time for STOP
condition
hold time (repeated)
START condition
set-up time for a
repeated START
condition
rise time of both SDA
and SCL signals
fall time of both SDA and
SCL signals
data valid acknowledge
time
data valid time
pulse width of spikes
that must be suppressed
by the input filter
is the minimum time for valid SDA (out) data following SCL LOW.
is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.
I
2
C-bus characteristics
f
.
13.2 I
f
for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, t
2
C-bus timing characteristics
[2][3][4]
[2][3][4]
[1]
[5]
[6]
[7]
SS
Standard mode
Min
0
4.7
4.0
250
0
4.7
4.0
4.0
4.7
-
-
0.1
300
-
to V
DD
Rev. 01 — 13 January 2010
(see
Max
100
-
-
-
-
-
-
-
-
1000
300
3.45
-
50
Figure
42).
Fast-mode (Fm)
Min
0
1.3
0.6
100
0
1.3
0.6
0.6
0.6
20 + 0.1C
20 + 0.1C
0.1
75
-
Integrated RTC, TCXO and quartz crystal
b
b
Max
400
-
-
-
-
-
-
-
-
300
300
0.9
-
50
Fast-mode Plus (Fm+) Unit
Min
0
0.5
0.26
50
0
0.5
0.26
0.26
0.26
-
-
0.05
75
-
IL
of the SCL signal) in order to
PCF2129A
f
is 250 ns. This allows
© NXP B.V. 2010. All rights reserved.
Max
1000
-
-
-
-
-
-
-
-
120
120
0.45
450
50
58 of 68
kHz
μs
μs
ns
ns
μs
μs
μs
μs
ns
ns
μs
ns
ns