PCF2113AU/10/F4 NXP [NXP Semiconductors], PCF2113AU/10/F4 Datasheet - Page 37
PCF2113AU/10/F4
Manufacturer Part Number
PCF2113AU/10/F4
Description
LCD controllers/drivers
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF2113AU10F4.pdf
(65 pages)
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NXP Semiconductors
PCF2113_FAM_4
Product data sheet
Fig 23. Example of 4-bit data transfer timing sequence
Fig 24. Example of busy flag checking timing sequence
IR7, IR3: instruction 7th, 3rd bit.
AC3: address counter 3rd bit.
D7, D3: data 7th, 3rd bit.
internal
R/W
DB7
RS
E
11.2 I
internal
R/W
DB7
RS
E
instruction
The I
The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines
must be connected to a positive supply via pull-up resistors. Data transfer may be initiated
only when the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH
level signal put on the bus by the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte.
2
write
C-bus interface
data
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
instruction
IR7
write
IR3
busy flag
internal operation
busy
check
internal operation
Rev. 04 — 4 March 2008
busy
busy flag
check
AC3
busy flag
check
busy
busy
not
busy flag
check
AC3
busy flag
check
busy
not
D7
instruction
write
D3
instruction
LCD controllers/drivers
data
write
PCF2113x
mga805
© NXP B.V. 2008. All rights reserved.
mga806
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