74LV4094D PHILIPS [NXP Semiconductors], 74LV4094D Datasheet - Page 2

• Manufacturer Part Number: 74LV4094D
• Description: 8-stage shift-and-store bus register
• Manufacturer: PHILIPS [NXP Semiconductors]

1.
Philips Semiconductors
FEATURES
Applications:
QUICK REFERENCE DATA
GND = 0 V; T
NOTE:
ORDERING INFORMATION
PIN CONFIGURATION
t
f
C
C
16-Pin Plastic DIL
16-Pin Plastic SO
1998 Jun 23
PHL
MAX
SYMBOL
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Output capability: standard
I
Serial-to-parallel data conversion
Remote control holding register
8-stage shift-and-store bus register
I
PD
CC
amb
amb
C
P
f
f
/t
i
o
category: MSI
D
PD
= input frequency in MHz; C
PLH
= output frequency in MHz; V
(C
= 25 C
= 25 C
= C
L
is used to determine the dynamic power dissipation (P
OLP
OHV
PD
PACKAGES
V
amb
CC
Propagation delay
CP to QS
CP to QS
CP to QP
STR to QP
Maximum clock frequency
Input capacitance
Power dissipation capacitance per gate
(output ground bounce) < 0.8 V at V
(output V
V
2
= 25 C; t
GND
CC
STR
QP
QP
QP
QP
CP
f
D
2
0
1
2
3
o
) = sum of the outputs.
2
3
4
5
6
7
8
1
2
n
1
f
OH
i
n
) (C
r
=t
undershoot) > 2 V at V
f
PARAMETER
2.5 ns
L
L
= output load capacity in pF;
CC
V
CC
CC
= supply voltage in V;
TEMPERATURE RANGE
2
= 2.7 V and V
16
15
14
12
11
10
13
SV01611
9
–40 C to +125 C
–40 C to +125 C
f
o
) where:
V
OE
QP
QP
QP
QP
QS
QS
CC
4
5
6
7
2
1
CC
CC
= 3.3 V,
= 3.3 V,
CC
= 3.6 V
C
V
V
V
CC
CC
I
L
= GND to V
D
= 15 pF;
in W)
= 3.3 V
= 3.3 V
OUTSIDE NORTH AMERICA
2
CONDITIONS
DESCRIPTION
The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT4094.
The 74LV4094 is an 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input (D) to the parallel buffered 3-State outputs (QP
parallel outputs may be connected directly to the common bus lines.
Data is shifted on the positive-going clock (CP) transitions. The data
in each shift register is transferred to the storage register when the
strobe input (STR) is HIGH. Data in the storage register appears at
the outputs whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS
number of 74LV4094 devices. Data is available at QS
positive-going clock edges to allow high-speed operation in
cascaded systems in which the clock rise time is fast. The same
serial information is available at QS
clock edge and is for cascading 74LV4094 devices when the clock
rise time is slow.
CC
PIN DESCRIPTION
PIN NUMBER
1
2
3
4, 5, 6, 7, 14,
13, 12, 11
8
9, 10
15
16
74LV4094 N
74LV4094 D
NO TAG
STR
D
CP
QP
GND
QS
OE
V
CC
SYMBOL
0
1
, QS
1
to QP
and QS
NORTH AMERICA
2
7
74LV4094 N
74LV4094 D
TYPICAL
2
) are available for cascading a
Strobe input
Serial input
Clock input
Parallel outputs
Ground (0 V)
Serial outputs
Output enable input
Positive supply voltage
3.5
2
14
13
18
17
95
83
on the next negative going
FUNCTION
Product specification
74LV4094
PKG. DWG. #
853-2078 19619
0
SOT109-1
SOT38-4
1
to OP
on the
UNIT
MHz
pF
pF
ns
7
). The