HSP48410/883 INTERSIL [Intersil Corporation], HSP48410/883 Datasheet
HSP48410/883
Related parts for HSP48410/883
HSP48410/883 Summary of contents
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... TM Data Sheet Histogrammer/Accumulating Buffer The Intersil HSP48410/883 lead Histogrammer IC int.ended for use in image and signal analysis. The on board memory is configured as 1024 x 24 array. This translates to a pixel resolution of 10 bits and an image size with no possibility of overflow. In addition to 4-Histogramming, the HSP48410 can generate and store the Cumulative Distribution Function for use in Histogram Equalization Applications ...
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... DIO18 DIO14 DIO15 DIO11 DIO12 DIO13 DIO8 GND DIO7 DIO5 DIO4 DIO3 DIO4 DIO2 DIO0 V IOADD1 HSP48410/883 84 PIN PGA TOP VIEW DIN11 DIN13 DIN16 DIN17 DIN19 DIN9 DIN12 DIN15 DIN21 DIN20 DIN14 GND DIN18 GND CLK PIN6 FCT0 IOADD9 ...
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... GND C7, E1, F9 HSP48410/883 TYPE I Clock Input. This input has no effect on the chips functionality when the chip is programmed to an asynchronous mode. All signals denoted as synchronous have their timing specified with reference to this signal. I Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on chip RAM with address values in Histogram, Bin Accumulate and LUT (write) mode ...
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... Power supply current is proportional to operating frequency. Typical rating for I considered when operating part at high clock frequencies. 4. Tested as follows 1MHz 2.6V Loading is as specified in the test load circuit with C 4 HSP48410/883 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V PGA Package Maximum Package Power Dissipation at 125 PGA Package ...
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... Output load circuit with C 7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. 8. Transition is measured at ±200 mV from steady state voltage with loading as specified in test load circuit with C 5 HSP48410/883 125 ...
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... Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with C CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D 6 HSP48410/883 CONDITIONS NOTES TEMP ( -55 ≤ -55 ≤ ...
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... Waveforms CLK DIN0-23 PIN0-9 DIO0-23 START FC FIGURE 1. SYNCHRONOUS DATA AND CONTROL TIMING LD FCT0-2 CLK START 7 HSP48410/883 FIGURE 2. FUNCTION LOAD TIMING t SH ...
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... Waveforms (Continued) RD DIO0- IOADD0-9 DIO0- IOADD0-9 DIO0-23 8 HSP48410/883 t OE FIGURE 3. SYNCHRONOUS OUTPUT TIMING FIGURE 4. WRITE CYCLE TIMING FIGURE 5. READ CYCLE TIMING t r 2.0V 0.8V FIGURE 6. OUTPUT RISE AND FALL TIMES WDS WDH ...
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... DIN1 CC 5 PIN8 PIN7 4 PIN5 PIN4 3 PIN3 PIN1 2 PIN2 FC 1 PIN0 START PIN “A1” HSP48410/883 84 PIN PGA TOP VIEW DIN11 DIN13 DIN16 DIN17 DIN19 DIN9 DIN12 DIN15 DIN21 DIN20 DIN14 GND DIN18 GND CLK PIN6 FCT0 IOADD9 IOADD8 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 HSP48410/883 TABLE 5. PIN BURN-IN ...