hsp48410 Intersil Corporation, hsp48410 Datasheet
hsp48410
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hsp48410 Summary of contents
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... Data Sheet Histogrammer/Accumulating Buffer The Intersil HSP48410 lead Histogrammer IC intended for use in image and signal analysis. The on-board memory is configured as 1024 x 24 array. This translates to a pixel resolution of 10 bits and an image size with no possibility of overflow. ...
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... DIO10 DIO13 DIO8 DIO9 GND DIO7 DIO6 DIO5 DIO4 DIO3 DIO1 DIO2 DIO0 IOADD0 V IOADD1 IOADD2 HSP48410 84 PGA TOP VIEW DIN11 DIN13 DIN16 DIN17 DIN19 DIN9 DIN12 DIN15 DIN21 DIN20 DIN14 GND DIN18 GND CLK PIN6 FCT0 IOADD9 IOADD8 ...
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... IOADD6 25 IOADD5 26 IOADD4 27 IOADD3 28 IOADD2 29 IOADD1 30 IOADD0 HSP48410 84 LEAD PLCC DIN8 73 DIN9 DIN10 72 DIN11 71 DIN12 70 DIN13 69 DIN14 68 DIN15 ...
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... DIO0-7 as being the upper eight bits of the data in or out of the Histogrammer. A zero means that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect. I Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one of the asynchronous modes. Asynchronous to CLK. I Read control for the data on DIO0-23 in asynchronous modes ...
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... For histogramming, this translates to an image size with 10-bit data. A Functional Block Diagram of the part is shown in Figure 1. In addition to histogramming, the HSP48410 will also perform Histogram Accumulation while feeding the results back into the memory array. The on-board RAM will then contain the Cumulative Distribution Function and can be used for further operation such as histogram equalization ...
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... RAM at the same address. RAM IN OUT WR ADDRESS “0” ADDRESS PIN 0-9 “1” GENERATOR START CONTROL FIGURE 2. HISTOGRAM MODE BLOCK DIAGRAM 6 HSP48410 24X1024 RAM IN OUT ADDRESS ADDER INPUT CONTROL ADDRESS GENERATOR COUNTER TO ADDRESS GENERATOR TO OUTPUT STAGE TO RAM MUX ...
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... RAM. When the START pin returns to a high state, the configuration remains intact, but writing to the 7 HSP48410 RAM is disabled and the part is in LUT(read) mode. Note that the counter is not reset at this point. The counter will be reset on the first cycle of CLK that START is detected low. To ...
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... OUT WR ADDRESS PIN 0-9 ADDRESS “0” GENERATOR CLK COUNTER START CONTROL FIGURE 8. LOOK UP TABLE BLOCK DIAGRAM 8 HSP48410 CLK START DATA 0 1 DIN 0-23 PIN 0-9 DIO 0-23 * PREVIOUS CONTENTS OF BIN LOCATION. FIGURE 9. LOOK UP TABLE MODE TIMING Delay Memory (Row Buffer) Mode As seen by comparing Figures 8 and 10, the configuration for this mode is nearly identical to the LUT mode ...
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... WR signal, while the read port always uses RD for latching. 9 HSP48410 The difference between the Async 16 mode and the Async 24 mode is the number of data bits available to the user. In 16-bit mode, the user can connect the system data bus to the lower 16 bits of the Histogrammer’ ...
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... Clock Period Clock Low Clock High DIN Setup DIN0-23 Hold Clock to DIO0-23 Valid FC Pulse Width FCT0-2 Setup HSP48410 Thermal Information Thermal Resistance (Typical, Note 3) +0.5V PGA Package PLCC Package Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Junction Temperature . . . . 175 Maximum Lead Temperature (Soldering 10s .300 ...
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... Characterized upon initial design and after major changes to design and/or process. 9. Transition is measured at 200mV from steady state voltage with loading as specified in test load circuit with C Test Load Circuit † INCLUDES STRAY AND JIG CAPACITANCE SWITCH S1 OPEN FOR I 11 HSP48410 5 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 12 HSP48410 t CL FCT0-2 ...