HSP45314VI INTERSIL [Intersil Corporation], HSP45314VI Datasheet - Page 12

• Manufacturer Part Number: HSP45314VI
• Description: CommLinkTM Direct Digital Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

Timing Diagrams
Pin Description
44-48, 1-3
PIN NO.
ANALOG OUT
35-38
42
40
30
27
32
REQUIRED WHILE RESET LOW
6
8
9
ANALOG OUT
ENOFR
ONE CLK RISING EDGE
CLK
RESET
FIGURE 5. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH)
CLK
PIN NAME
UPDATE
RESET
DGND
DGND
DGND
C(7:0)
A(3:0)
CLK
WR
WE
(Continued)
3-12
(Input)
(Input)
(Input)
TYPE
Clock
Input
Input
Input
Input
Input
Input
t
ES
t
EL
CENTER FREQUENCY ONLY
t
RS
= 14 CLK RISING EDGES
8-bit Processor Input Data Bus. C7 is the MSB. Data is written to the control register selected on
A(3:0) on the rising edge of WR when WE is active.
Write Clock For The Processor Interface. Parallel data is clocked into the chip on the rising edge
of WR.
Write Enable. Active low. WE must be active when writing data to the chip.
Processor Interface Address Bus. These pins select the destination register for data on the C(7:0)
bus. A3 is the MSB.
NCO and DAC Clock. The phase accumulator and DAC output update on the rising edge of this
clock. CLK can be asynchronous to the WR clock.
Reset. Active Low. Resets control registers to their default states (see register description table)
and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur.
Connect to DGND. Future serial clock input.
Connect to DGND. Future serial data input.
Connect to DGND. Future serial sync input.
Active Low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0)
pins. This pin is provided for updating an entire frequency word at once rather than byte by byte.
FIGURE 4. RESET TIMING AND LATENCY
t
RL
= 11 CLK RISING EDGES
HSP45314
t
EH
PREVIOUS REGISTER VALUES
CENTER + OFFSET
PIN DESCRIPTION
RESET REGISTER VALUES
CENTER ONLY
CENTER
+ OFFSET