HSP45314VI INTERSIL [Intersil Corporation], HSP45314VI Datasheet
HSP45314VI
Related parts for HSP45314VI
HSP45314VI Summary of contents
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... Parallel Control Interface for Fast Tuning (50MSPS Control Register Write Rate) • 48-bit Programmable Frequency Control • Small 48-pin LQFP package Applications • Programmable Local Oscillator • FSK Modulation • Direct Digital Synthesis • Clock Generation Ordering Information PART NUMBER HSP45314VI Pinout IN IN+ COMP1 COMP2 14 BIT IOUTA C2 DAC ...
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Typical Application Circuit (Sinewave Generation) PROCESSOR/ FPGA/CPLD CLOCK SOURCE DV PP 0.1 F +5V POWER SOURCE 3-2 HSP45314 WRITE CLOCK WRITE ENABLE PH1:PH0 BUS A3:A0 BUS C7:C0 BUS ...
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Functional Description The HSP45314 is an NCO with an integrated 14-bit DAC designed to run in excess of 125MSPS. The NCO is a 16-bit output design, which is rounded to 14 bits for input to the DAC. The frequency control ...
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Control Pins There are three control pins provided for phase and frequency control. The PH0 and PH1 pins select phase offsets of 0, 90, 180, and 270 degrees and can be used for low speed, unfiltered BPSK or QPSK modulation. ...
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The necessity to have a 50 impedance looking back into the transformer is negated if the DDS is only driving a short trace. The output ...
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Absolute Maximum Ratings Digital Supply Voltage DV to DGND . . . . . . . . . . . . . . . . . . +5.5V DD Analog Supply Voltage AV to AGND . . . . . ...
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Electrical Specifications PARAMETER AC CHARACTERISTICS Spurious Free Dynamic Range, f CLK SFDR Within a Window (Notes CLK f CLK Spurious Free Dynamic Range, f CLK SFDR to Nyquist (f /2) (Notes ...
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Electrical Specifications PARAMETER TIMING CHARACTERISTICS Maximum Clock Rate, f +5V DV CLK Maximum Clock Rate, f +3.3V DV CLK CLK Pulse Width, t CLK (Note 3) CW Maximum Parallel Write Rate Rate of WR ...
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Electrical Specifications PARAMETER COMPARATOR CHARACTERISTICS Input Capacitance Input Resistance Input Current Maximum Input Voltage Allowed (Excluding comparator sleep mode) Minimum Input Voltage, Peak-to-Peak (Dependent on noise) Propagation Delay, High to Low (Note 8) Propagation ...
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Definition of Specifications Differential Non-Linearity, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1LSB. A DNL specification of 1LSB or less guarantees monotonicity. Integral Non-Linearity, INL, is the ...
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Timing Diagrams ADDR ADDR A0 DATA WRITE CLK UPDATE ANALOG OUT FIGURE 2. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH ADDR A0 DATA ...
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Timing Diagrams (Continued) ONE CLK RISING EDGE REQUIRED WHILE RESET LOW CLK RESET ANALOG OUT CLK ENOFR ANALOG OUT FIGURE 5. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH) Pin Description PIN NO. PIN NAME TYPE 44-48, ...
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Pin Description (Continued) PIN NO. PIN NAME TYPE 33, 34 PH(1:0) Input 4 ENOFR Input 10 COMPOUT Output 11 REFLO Input 12 REFIO Input 13 FSADJ 14 COMP1 19 COMP2 18 IOUTA Output 17 IOUTB Output 20 AV Power DD ...
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Control Register Description ADDRESS BITS 12 7:1 Bits 7 through 1 are Intersil reserved for future serial input control. Do Not Change. 0 Center Frequency Enable enable center frequency disabled. This bit can be used to ...