HSP45314VI INTERSIL [Intersil Corporation], HSP45314VI Datasheet

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HSP45314VI

Manufacturer Part Number
HSP45314VI
Description
CommLinkTM Direct Digital Synthesizer
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
CommLink
The 14-bit HSP45314 provides a complete Direct Digital
Synthesizer (DDS) system in a single 48-pin LQFP package.
A 48-bit Programmable Carrier NCO (numerically controlled
oscillator) and a high speed 14-bit DAC (digital to analog
converter) are integrated into a stand alone DDS.
The DDS accepts 48-bit center and offset frequency control
information via a parallel processor interface. Modulation
control is provided by 3 external pins. The PH0 and PH1 pins
select phase offsets of 0, 90, 180 and 270 degrees, while the
ENOFR pin enables or zeros the offset frequency word to
the phase accumulator.
The parallel processor interface has an 8-bit write-only data
input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe
(WR), and a Write Enable (WE). The processor can update
all registers simultaneously by loading a set of master
registers, then transfer all master registers to the slave
registers by asserting the UPDATE pin.
Block Diagram
UPDATE
ENOFR
PH(1:0)
RESET
C(7:0)
A(3:0)
CLK
WR
WE
TM
Direct Digital Synthesizer
TM
3-1
ACCUM.
PHASE
WAVE
SINE
ROM
1-888-INTERSIL or 321-724-7143
Data Sheet
14 BIT
DAC
INT
REF
-
+
IN-
IN+
COMP1
COMP2
IOUTA
IOUTB
REFIO
REFLO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
Intersil and Design is a trademark of Intersil Corporation.
Features
• 125MSPS Output Sample Rate with 5V Digital Supply
• 100MSPS Output Sample Rate with 3.3V Digital Supply
• 14-bit DAC with Internal Reference
• Parallel Control Interface for Fast Tuning (50MSPS Control
• 48-bit Programmable Frequency Control
• Small 48-pin LQFP package
Applications
• Programmable Local Oscillator
• FSK Modulation
• Direct Digital Synthesis
• Clock Generation
Ordering Information
Pinout
HSP45314VI
COMPOUT
Register Write Rate)
UPDATE
NUMBER
ENOFR
REFLO
RESET
REFIO
DGND
DVDD
PART
CLK
C2
C1
C0
May 2000
TEMP. RANGE
1
2
3
4
5
6
10
11
12
7
8
9
48
13 14 15 16
48-PIN LQFP (Q48.7X7A
-40 to 85
47
(
o
46
C)
CommLink™ is a trademark of Intersil Corporation.
45
TOP VIEW
44
17
HSP45314
43
18
48 LQFP
|
42
19
File Number
PACKAGE
Copyright
41
20
40
21
HSP45314
22
39
©
23
38
Intersil Corporation 2000
37
24
Q48.7X7A
36
35
34
33
32
31
30
29
28
27
26
25
PKG. NO.
4820.2
A2
A3
PH0
PH1
DGND
DVDD
DGND
DGND
DGND
DGND
DVDD
DGND

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HSP45314VI Summary of contents

Page 1

... Parallel Control Interface for Fast Tuning (50MSPS Control Register Write Rate) • 48-bit Programmable Frequency Control • Small 48-pin LQFP package Applications • Programmable Local Oscillator • FSK Modulation • Direct Digital Synthesis • Clock Generation Ordering Information PART NUMBER HSP45314VI Pinout IN IN+ COMP1 COMP2 14 BIT IOUTA C2 DAC ...

Page 2

Typical Application Circuit (Sinewave Generation) PROCESSOR/ FPGA/CPLD CLOCK SOURCE DV PP 0.1 F +5V POWER SOURCE 3-2 HSP45314 WRITE CLOCK WRITE ENABLE PH1:PH0 BUS A3:A0 BUS C7:C0 BUS ...

Page 3

Functional Description The HSP45314 is an NCO with an integrated 14-bit DAC designed to run in excess of 125MSPS. The NCO is a 16-bit output design, which is rounded to 14 bits for input to the DAC. The frequency control ...

Page 4

Control Pins There are three control pins provided for phase and frequency control. The PH0 and PH1 pins select phase offsets of 0, 90, 180, and 270 degrees and can be used for low speed, unfiltered BPSK or QPSK modulation. ...

Page 5

The necessity to have a 50 impedance looking back into the transformer is negated if the DDS is only driving a short trace. The output ...

Page 6

Absolute Maximum Ratings Digital Supply Voltage DV to DGND . . . . . . . . . . . . . . . . . . +5.5V DD Analog Supply Voltage AV to AGND . . . . . ...

Page 7

Electrical Specifications PARAMETER AC CHARACTERISTICS Spurious Free Dynamic Range, f CLK SFDR Within a Window (Notes CLK f CLK Spurious Free Dynamic Range, f CLK SFDR to Nyquist (f /2) (Notes ...

Page 8

Electrical Specifications PARAMETER TIMING CHARACTERISTICS Maximum Clock Rate, f +5V DV CLK Maximum Clock Rate, f +3.3V DV CLK CLK Pulse Width, t CLK (Note 3) CW Maximum Parallel Write Rate Rate of WR ...

Page 9

Electrical Specifications PARAMETER COMPARATOR CHARACTERISTICS Input Capacitance Input Resistance Input Current Maximum Input Voltage Allowed (Excluding comparator sleep mode) Minimum Input Voltage, Peak-to-Peak (Dependent on noise) Propagation Delay, High to Low (Note 8) Propagation ...

Page 10

Definition of Specifications Differential Non-Linearity, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1LSB. A DNL specification of 1LSB or less guarantees monotonicity. Integral Non-Linearity, INL, is the ...

Page 11

Timing Diagrams ADDR ADDR A0 DATA WRITE CLK UPDATE ANALOG OUT FIGURE 2. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH ADDR A0 DATA ...

Page 12

Timing Diagrams (Continued) ONE CLK RISING EDGE REQUIRED WHILE RESET LOW CLK RESET ANALOG OUT CLK ENOFR ANALOG OUT FIGURE 5. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH) Pin Description PIN NO. PIN NAME TYPE 44-48, ...

Page 13

Pin Description (Continued) PIN NO. PIN NAME TYPE 33, 34 PH(1:0) Input 4 ENOFR Input 10 COMPOUT Output 11 REFLO Input 12 REFIO Input 13 FSADJ 14 COMP1 19 COMP2 18 IOUTA Output 17 IOUTB Output 20 AV Power DD ...

Page 14

Control Register Description ADDRESS BITS 12 7:1 Bits 7 through 1 are Intersil reserved for future serial input control. Do Not Change. 0 Center Frequency Enable enable center frequency disabled. This bit can be used to ...

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