TSA5514AT PHILIPS [NXP Semiconductors], TSA5514AT Datasheet - Page 7

• Manufacturer Part Number: TSA5514AT
• Description: 1.3 GHz bidirectional I2C-bus controlled synthesizer
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
READ mode: R/W = 1 (see Table 2)
Data can be read out of the TSA5514 by setting the R/W
bit to 1. After the slave address has been recognized, the
TSA5514 generates an acknowledge pulse and the first
data byte (status word) is transferred on the SDA line
(MSB first). Data is valid on the SDA line during a high
position of the SCL clock signal.
A second data byte can be read out of the TSA5514 if the
processor generates an acknowledge on the SDA line.
End of transmission will occur if no acknowledge from the
processor occurs.
The TSA5514 will then release the data line to allow the
processor to generate a STOP condition.
When ports P4 to P7 are used as inputs, they must be
programmed in their high-impedance state.
The POR flag (power-on reset) is set to 1 when V
Table 2 Read data format
MSB is transmitted first.
Address selection
The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several
synthesizers (up to 4) in one system.
The relationship between MA1 and MA0 and the input voltage on AS pin is given in Table 4.
October 1992
Address
Status byte
POR
FL
I2, I1, I0
A2, A1, A0
1.3 GHz bidirectional I
power-on reset flag. (POR = 1 on power-on)
in-lock flag (FL = 1 when the loop is phase-locked)
digital information for I/O ports P7, P5 and P4 respectively
digital outputs of the 5-level ADC. Accuracy is 1/2 LSB (see Table 3)
MSB
POR
1
2
FL
C-bus controlled synthesizer
1
I2
0
cc
goes
I1
0
7
below 3 V and at power-on. It is reset when an end of data
is detected by the TSA5514 (end of a READ sequence).
Control of the loop is made possible with the in-lock flag FL
which indicates (FL = 1) when the loop is phase-locked.
The bits I2, I1 and I0 represent the status of the I/O ports
P7, P5 and P4 respectively. A logic 0 indicates a LOW
level and a logic 1 a HIGH level (TTL levels).
A built-in 5-level ADC is available on I/O port P6. This
converter can be used to feed AFC information to the
controller from the IF section of the television as illustrated
in the typical application circuit (Fig.8). The relationship
between bits A2, A1 and A0 and the input voltage on port
P6 is given in Table 3.
I0
0
MA1
A2
MA0
A1
LSB
A0
1
A
Product specification
TSA5514
byte 1
byte 2