HD74AC HITACHI [Hitachi Semiconductor], HD74AC Datasheet - Page 30

• Manufacturer Part Number: HD74AC
• Description: HD74AC Series Common Information
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6 AC Characteristics
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
max
TLH
THL
PLH
PHL
HZ
LZ
ZH
ZL
w
h
SU
Term
Maximum clock frequency
Rise (transient) time
Fall (transient) time
Output rise propagation delay time
Output fall propagation delay time
3-state output disable time (high level)
3-state output disable time (low level)
3-state output enable time (high level)
3-state output enable time (low level)
Pulse width
Hold time
Setup time
Description
Maximum clock frequency that maintains the stable
changes in output logic level in the rated sequence
under the I/O condition allowing clock pulses to
change the output state
Rated time from low level to high level of a
wavefrom during the defined transient period
changing from low level to high level
Rated time from high level to low level of a
wavefrom during the defined transient period
changing from high level to low level
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the output changing from low level
to high level
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the output changing from high level
to low level
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from
high level to the high-impendance state
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from low
level to the high-impendance state
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from the
high-impendance state to high level
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from the
high-impendance state to low level
Duration of time between the rated levels from a
leading edge to a trailing edge of a pulse waveform
Time in which to hold data at the specified input
terminal after a change at another related input
terminal (e.g., clock input)
Time in which to set up and keep data at the
specified input terminal before a change at another
related input terminal (e.g., clock input)
Definition of Specifications
29