CY7C68000A CYPRESS [Cypress Semiconductor], CY7C68000A Datasheet - Page 12

• Manufacturer Part Number: CY7C68000A
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08052 Rev. *F
Package Diagrams
Figure 7. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56
PCB Layout Recommendations
The following recommendations must be followed to ensure
reliable high-performance operation.
Note
• At least a four-layer impedance controlled board is required
• Specify impedance targets (ask your board vendor what
• To control impedance, maintain trace widths and trace
• Minimize stubs to minimize reflected signals
• Connections between the USB connector shell and signal
• Bypass/flyback capacitors on VBus, near the connector, are
3. Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf High-
to maintain signal quality
they can achieve)
spacing to within written specifications
ground must be done near the USB connector
recommended
Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
PIN A1 CORNER
A
C
G
B
D
E
F
H
-C-
1
SEATING PLANE
2
SIDE VIEW
(continued)
5.00±0.10
3
TOP VIEW
4
5
6
6
8
[3]
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
• DPLUS and DMINUS trace lengths must be kept to within
• Maintain a solid ground plane under the DPLUS and
• It is best to have no vias placed on the DPLUS or DMINUS
• Isolate the DPLUS and DMINUS traces from all other signal
2 mm of each other in length, with preferred length of 20–30
mm
DMINUS traces. Do not allow the plane to be split under
these traces
trace routing
traces by no less than 10 mm
PACKAGE WEIGHT: 0.02 grams
REFERENCE JEDEC: MO-195C
-B-
0.10(4X)
-A-
BOTTOM VIEW
8
7
Ø0.05 M C
Ø0.15 M C A B
Ø0.30±0.05(56X)
6
5.00±0.10
5
0.50
3.50
4
001-03901-*B
3
CY7C68000A
2
1
A1 CORNER
A
B
C
D
E
F
G
H
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