CY7C4281V-15JI CYPRESS [Cypress Semiconductor], CY7C4281V-15JI Datasheet - Page 9

• Manufacturer Part Number: CY7C4281V-15JI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06013 Rev. *B
Switching Waveforms
Reset Timing
WEN2/LD
Notes:
14. The clocks (RCLK, WCLK) can be free-running during reset.
15. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
16. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
Q
EF,PAE
FF, PAF
REN1,
WEN1
0 −
REN2
RS
[16]
Q
8
[14]
(continued)
t
t
t
RSF
RSF
RSF
t
RS
t
t
t
RSS
RSS
RSS
t
t
t
RSR
RSR
RSR
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
OE=0
OE = 1
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