CY7C4281V-15JI CYPRESS [Cypress Semiconductor], CY7C4281V-15JI Datasheet - Page 12

• Manufacturer Part Number: CY7C4281V-15JI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06013 Rev. *B
Switching Waveforms
Full Flag Timing
Programmable Almost Empty Flag Timing
Notes:
19. t
20. PAE offset = n.
21. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
(if applicable)
(if applicable)
WCLK and the rising RCLK is less than t
SKEW2
WEN2
WEN2
Q
D
WCLK
WEN1
REN1,
WCLK
REN1,
RCLK
WEN1
REN2
RCLK
0
0
REN2
PAE
–D
–Q
OE
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
FF
8
8
DATA IN OUTPUT REGISTER
t
t
LOW
SKEW1
CLKH
[12]
t
ENS
NO WRITE
(continued)
t
SKEW2
SKEW2
t
WFF
t
t
A
ENH
t
t
, then PAE may not change state until the next RCLK.
ENS
ENS
[19]
t
t
ENH
ENH
t
CLKL
t
DS
Note
t
PAE
20
DATA WRITE
DATA READ
t
ENS
t
WFF
t
SKEW1
N + 1 WORDS
t
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
[12]
ENS
IN FIFO
t
ENS
NO WRITE
t
ENH
t
WFF
t
t
A
ENH
NEXT DATA READ
Note21
Page 12 of 16
DATA WRITE
t
PAE