CAT5271ZI-00-GT3 ONSEMI [ON Semiconductor], CAT5271ZI-00-GT3 Datasheet
CAT5271ZI-00-GT3
Related parts for CAT5271ZI-00-GT3
CAT5271ZI-00-GT3 Summary of contents
Page 1
CAT5271 Dual 256-Position I Compatible Digital Potentiometer The CAT5271 is a dual 256−position digitally programmable linear taper potentiometer ideally suited for replacing mechanical potentiometers and variable resistors. The wiper settings are controlled through an I interface. Upon power−up, the wiper ...
Page 2
... Table 1. ORDERING INFORMATION Part Number Resistance CAT5271ZI−50−GT3 50 kW CAT5271ZI−00−GT3 100 kW †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Table 2. PIN FUNCTION DESCRIPTION Pin No. ...
Page 3
Table 4. ELECTRICAL CHARACTERISTICS and 100 kW Versions –40°C < Parameter DC CHARACTERISTICS — RHEOSTAT MODE Resistor Differential ...
Page 4
Table 5. CAPACITANCE T = 25° 1.0 MHz Symbol C Input/Output Capacitance (SDA, SCL) I/O (Note 11) Table 6. POWER UP TIMING (Notes 11 and 12) Symbol t Power−up to Read Operation ...
Page 5
DNL 0.01 0 −0.01 −0.02 −0.03 −0.04 −0. 128 160 TAP Figure 2. Differential Non−Linearity 5 120 100 5.6 V ...
Page 6
TEMPERATURE (°C) Figure 7. Change in End−to−End Resistance 0 −6 V − −18 −24 −30 − (KHz) Figure 9. Gain vs. Bandwidth (Tap 0x80) ...
Page 7
Basic Operation The CAT5271 is a dual 256−position digitally controlled potentiometer. When power is first applied, the wipers assume a mid−scale position. Once the power supply is stable, the wipers may be repositioned via the I compatible interface. Programming: Variable ...
Page 8
ESD Protection Digital LOGIC Input GND Potentiometer GND Figure 12. ESD Protection Networks Terminal Voltage Operating Range The CAT5271 V and GND power supply define the DD limits for proper 3−terminal digital potentiometer operation. Signals or potentials ...
Page 9
I C Bus Protocol The following defines the features of the I 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock ...
Page 10
SDA SCL START CONDITION SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START Figure 16. Start/Stop Condition 1 Figure 17. Acknowledge Condition http://onsemi.com 10 STOP CONDITION 8 9 ACKNOWLEDGE ...
Page 11
INSTRUCTION AND REGISTER DESCRIPTION SLAVE ADDRESS BYTE The first byte sent to the CAT5271 from the master/processor is called the Slave Address Byte. The most significant seven bits of the slave address are a device type identifier. For the CAT5271, ...
Page 12
E E1 TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. PACKAGE DIMENSIONS MSOP 10, 3x3 CASE 846AE−01 ISSUE O SYMBOL MIN A A1 0.00 ...
Page 13
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for ...