CY7C429 CYPRESS [Cypress Semiconductor], CY7C429 Datasheet - Page 8

• Manufacturer Part Number: CY7C429
• Description: 64K/128K x 9 Deep Sync FIFOs
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06007 Rev. *B
Switching Waveforms
Notes:
13. t
14. t
REN1, REN2
Read Cycle Timing
REN1, REN2
Write Cycle Timing
edge of RCLK and the rising edge of WCLK is less than t
edge of WCLK and the rising edge of RCLK is less than t
(if applicable)
SKEW1
SKEW1
Q
D
WEN2
0
0
WEN1
WCLK
WEN1
WEN2
WCLK
RCLK
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising
RCLK
–D
–Q
OE
EF
FF
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
CLKH
CLKH
[ 13 ]
t
t
t
WFF
A
REF
t
SKEW1
SKEW2
OE
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
t
t
CLK
CKL
t
SKEW1
NO OPERATION
[ 14 ]
t
DS
t
t
CLKL
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
NO OPERATION
NO OPERATION
CY7C4281
CY7C4291
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