CY7C344 CYPRESS [Cypress Semiconductor], CY7C344 Datasheet - Page 3

• Manufacturer Part Number: CY7C344
• Description: 32-Macrocell MAX EPLD
• Manufacturer: CYPRESS [Cypress Semiconductor]

Timing Delays
Timing delays within the CY7C344 may be easily determined
using Warp™, Warp Professional™, or Warp Enterprise™
software. The CY7C344 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause per-
manent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
data sheet is not implied. Exposure to absolute maximum rat-
ings conditions for extended periods of time may affect device
reliability. The CY7C344 contains circuitry to protect device
pins from high-static voltages or electric fields; however, normal
precautions should be taken to avoid applying any voltage high-
er than maximum rated voltages.
For proper operation, input and output pins must be con-
strained to the range GND (V
must always be tied to an appropriate logic level (either V
Each set of V
at the device. Power supply decoupling capacitors of at least 0.2 F
must be connected between V
decoupling, each V
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay t
When calculating synchronous frequencies, use t
are on the input pins. t
pin. If t
in the data-path mode unless 1/(t
Document #: 38-03006 Rev. **
S2
INPUT
I/O
is greater than t
CC
EXP
and GND pins must be connected together directly
CC
to the overall delay.
I/O DELAY
S2
DELAY
INPUT
pin should be separately decoupled.
I/O
t
t
IN
IO
CO1
should be used if data is applied at an I/O
, 1/t
CC
WH
S2
IN
and GND. For the most effective
or V
becomes the limiting frequency
+ t
WL
OUT
) is less than 1/t
) V
SYSTEM CLOCK DELAYt
CC
Figure 1. CY7C344 Timing Model.
CONTROLDELAY
. Unused inputs
LOGIC ARRAY
LOGIC ARRAY
EXPANDER
S1
DELAY
CC
CLOCK
DELAY
t
DELAY
t
if all inputs
t
EXP
LAD
S2
LAC
t
or GND).
IC
.
t
t
t
t
CLR
PRE
RSU
RH
ICS
FEEDBACK
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
1/(t
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
t
an I/O pin, t
t
quency in the data-path mode unless 1/(t
1/(t
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
of 1/(t
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter t
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If t
than the minimum required input hold time of the subsequent syn-
chronous logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case environmental
and supply voltage conditions.
The parameter t
vice when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344. In general, if t
is greater than the minimum required input hold time of the subse-
quent logic (synchronous or asynchronous), then the devices are
guaranteed to function properly under worst-case environmental and
supply voltage conditions, provided the clock signal source is the
same. This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This is due to
the expander logic in the second device’s clock signal path adding an
additional delay (t
device to change prior to the arrival of the clock signal at the following
device’s register.
AH
AS1
DELAY
WH
AS2
) is greater than t
t
FD
if all inputs are on dedicated input pins. If any data is applied to
AWH
+ t
+ t
REGISTER
WL
AH
+ t
t
t
LATCH
COMB
AS2
t
RD
), 1/t
).
AWL
must be used as the required set-up time. If (t
CO1
), 1/t
OH
EXP
AOH
ACO1
ACO1
indicates the system compatibility of this device
, or 1/(t
), causing the output data from the preceding
indicates the system compatibility of this de-
, 1/(t
, or 1/(t
C344–7
EXP
AS2
OUTPUT
DELAY
+ t
EXP
t
t
t
OD
XZ
ZX
+ t
S1
EXP
+ t
EXP
) is the lowest frequency. The
AH
AS1
) becomes the limiting fre-
to t
AWH
to t
) is the lowest frequency.
S1
AS1
. Determine which of
+ t
OUTPUT
. Determine which
AWL
CY7C344
Page 3 of 15
) is less than
OH
is greater
AS2
AOH
+