HEF4035BF PHILIPS [NXP Semiconductors], HEF4035BF Datasheet - Page 2

• Manufacturer Part Number: HEF4035BF
• Description: 4-bit universal shift register
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
DESCRIPTION
The HEF4035B is a fully synchronous edge-triggered 4-bit
shift register with a clock input (CP), four synchronous
parallel data inputs (P
inputs (J, K), a synchronous parallel enable input (PE),
buffered parallel outputs from all 4-bit positions (O
a true/complement input (T/C) and an overriding
asynchronous master reset input (MR). Each register is of
a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is
edge-triggered on the LOW to HIGH transition of the CP
input. When PE is HIGH, data is loaded into the register
from P
FAMILY DATA, I
See Family Specifications
January 1995
4-bit universal shift register
0
to P
3
on the LOW to HIGH transition of CP.
DD
LIMITS category MSI
0
to P
3
), two synchronous serial data
Fig.1 Functional diagram.
0
to O
3
),
2
When PE is LOW, data is shifted into the first register
position from J and K and all the data in the register is
shifted one position to the right on the LOW to HIGH
transition of CP. D-type entry is obtained by
interconnecting J and K. When J = HIGH and K = LOW the
first stage is in the toggle mode. When J = LOW and
K = HIGH the first stage is in the hold mode.
The outputs (O
depending on T/C state. With T/C HIGH, O
non-inverting (active HIGH) and when T/C is LOW, O
O
A HIGH on MR resets all four bit positions (O
O
independent of all other input conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
3
3
are inverting (active LOW).
= LOW if T/C = HIGH, O
0
to O
3
) are either inverting or non-inverting,
0
to O
3
Product specification
= HIGH if T/C = LOW)
HEF4035B
0
to O
0
to
3
MSI
are
0
to