CY7C1518AV18-278BZI CYPRESS [Cypress Semiconductor], CY7C1518AV18-278BZI Datasheet - Page 10

• Manufacturer Part Number: CY7C1518AV18-278BZI
• Description: 72-Mbit DDR-II SRAM 2-Word Burst Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Truth Table
The truth table for the CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and CY7C1520AV18 follow.
Burst Address Table
(CY7C1518AV18, CY7C1520AV18)
Write Cycle Descriptions
The write cycle description table for CY7C1516AV18 and CY7C1518AV18 follows.
Notes
Document Number: 001-06982 Rev. *C
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. On CY7C1518AV18 and CY7C1520AV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. Is based on a write cycle that was initiated in accordance with the
BWS
NWS
H
H
H
H
sequence in the burst. On CY7C1516AV18 and CY7C1527AV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.
symmetrically.
different portions of a write cycle, as long as the setup and hold requirements are achieved.
L
L
L
L
0
0
/
BWS
NWS
H
H
H
H
L
L
L
L
1
1
/
L–H
L–H
L–H
L–H
First Address (External)
K
–
–
–
–
Operation
L–H During the data portion of a write sequence :
L–H During the data portion of a write sequence :
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence :
K
–
–
–
–
X..X0
X..X1
During the data portion of a write sequence :
CY7C1516AV18 − both nibbles (D
CY7C1518AV18 − both bytes (D
CY7C1516AV18 − both nibbles (D
CY7C1518AV18 − both bytes (D
During the data portion of a write sequence :
CY7C1516AV18 − only the lower nibble (D
CY7C1518AV18 − only the lower byte (D
CY7C1516AV18 − only the lower nibble (D
CY7C1518AV18 − only the lower byte (D
During the data portion of a write sequence :
CY7C1516AV18 − only the upper nibble (D
CY7C1518AV18 − only the upper byte (D
CY7C1516AV18 − only the upper nibble (D
CY7C1518AV18 − only the upper byte (D
No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
Stopped
L-H
L-H
L-H
K
[17:0]
[17:0]
[7:0]
[7:0]
) are written into the device.
) are written into the device.
) are written into the device,
) are written into the device,
[8:0]
[8:0]
LD
[17:9]
[17:9]
H
L
L
X
[3:0]
[3:0]
[7:4]
[7:4]
table. NWS
Comments
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
CY7C1516AV18, CY7C1527AV18
CY7C1518AV18, CY7C1520AV18
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
R/W
[2, 8]
0
H
, NWS
L
X
X
Second Address (Internal)
1
, BWS
D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
High-Z
Previous State
0
X..X1
X..X0
, BWS
DQ
1
, BWS
[17:9]
[17:9]
[2, 3, 4, 5, 6, 7]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
2
, and BWS
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
High-Z
Previous State
3
can be altered on
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DQ
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