AD9518-0A-PCBZ AD [Analog Devices], AD9518-0A-PCBZ Datasheet - Page 59

• Manufacturer Part Number: AD9518-0A-PCBZ
• Description: 6-Output Clock Generator
• Manufacturer: AD [Analog Devices]

Data Sheet
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9518
The
settings and version of the AD9518, keep in mind the following
guidelines.
The
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
Within the
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the
frequency plan can be achieved with a version of the
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter.
However, choosing a higher VCO frequency may result in more
flexibility in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9518 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.
AD9518
AD9518
AD9518
is a highly flexible PLL. When choosing the PLL
has the following four frequency dividers: the
family, lower VCO frequencies generally
AD9518
family. If the desired
AD9518
Rev. C | Page 59 of 64
Considering an ideal ADC of infinite resolution where the step
size and quantization error can be ignored, the available SNR
can be expressed approximately by
where:
f
t
Figure 52 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
For more information, see the
Systems and the Effects of Clock Phase Noise and Jitter; and the
AN-501
Performance, at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can provide
superior clock performance in a noisy environment.) The
features LVPECL outputs that provide differential clock outputs,
which enable clock solutions that maximize converter SNR
performance. The input requirements of the ADC (differential
or single-ended, logic level, termination) should be considered
when selecting the best clocking/converter solution.
A
J
is the rms jitter on the sampling clock.
is the highest analog frequency being digitized.
110
100
90
80
70
60
50
40
30
SNR
10
Application Note, Aperture Uncertainty and ADC System
(
Figure 52. SNR and ENOB vs. Analog Input Frequency
dB
)
=
20
×
log




2
π
1
f
f
A
A
AN-756
100
t
(MHz)
J




SNR = 20log
Application Note, Sampled
2πf
1
A
AD9518-0
t
J
1k
AD9518
18
16
14
12
10
8
6